Contents

What Changed

A September 2, 2026 Tom's Hardware feature consolidates where copper-to-copper hybrid bonding actually stands, and the picture is not a bottleneck — it is a gap between what the process can do and what products are buying. TSMC has scaled its SoIC bond pitch from 9 µm to 6 µm and published a path to 4.5 µm by 2029. Intel shipped Foveros Direct in volume in the Clearwater Forest Xeon 6+ during the first half of 2026 — at 9 µm, with a 3 µm second generation on its roadmap.

Meanwhile the market everyone expected to consume hybrid bonding in quantity has bought itself another generation on solder. A January 2026 JEDEC decision raising the HBM package height ceiling from 720 µm to 775 µm let 16-high HBM4 be assembled with microbumps after all, deferring hybrid bonding's memory debut to HBM4E and HBM5.

The result: capability is running ahead of adoption, and the equipment commitments are running ahead of both.

The Pitch Ladder: 40 µm to 200 nm

Microbumps have historically run near 40 µm pitch, tightening toward 10 µm for the latest memory. Hybrid bonding starts where microbumps stop and keeps going: 6 µm at the leading edge today, 4.5 µm and 3 µm generations in development, and sub-micron pitches demonstrated in research.

The research figures set the ceiling. At ECTC in May, imec and EV Group demonstrated a 200 nm wafer-to-wafer pitch with post-bond overlay below 40 nm. The best die-to-wafer pitch shown at ECTC 2026, from CEA-Leti, was 1 µm — roughly five times looser than the wafer-to-wafer record.

Density is the payoff. Figures presented at TSMC's 2026 North America Technology Symposium put face-to-face hybrid bonding at roughly 14,000 signals per square millimeter against about 1,500 for face-to-back stacking, where signals must still route through through-silicon vias in the lower die. AMD has cited approximately 15× the interconnect density of conventional 2.5D microbump stacking. TSMC's node-stacking roadmap runs in parallel with the pitch roadmap, from N3P-on-N4 today toward N2P-on-N2P by 2028 and A14-on-A14 in 2029, the last of which TSMC says delivers 1.8× the die-to-die I/O density of N2-on-N2 SoIC.

Whether that density is worth its cost at a given pitch is exactly the calculation covered in our comparison of hybrid bonding versus micro-bump interconnect — the pitch zones where each wins, and where the crossover sits.

Wafer-to-Wafer vs. Die-to-Wafer: The Throughput Tax

The two integration formats are not interchangeable, and the ECTC numbers show why. Wafer-to-wafer bonding joins two full patterned wafers face-to-face and dices afterward. Alignment happens once at wafer scale, which is why it holds the tightest pitch record and the fastest throughput. The constraint is that both wafers must carry identically sized dies, and every die gets bonded — including defective ones, so one bad die ruins its pair.

Die-to-wafer places individual, pre-tested dies onto a wafer. That is what chiplet and HBM stacks require, because it permits known-good-die selection and mixing die sizes and process nodes. The penalty is sequential placement: Applied Materials and Besi cite roughly 1,600 die placements per hour on the Kinex platform, and Besi's Chameo bonders are rated near 2,000 chips per hour, with the next generation targeting 50 nm placement accuracy to reach finer pitches. The bonder's rate, not the bond physics, sets the output limit.

That trade — geometry, yield, throughput, density — is the four-gate decision we walk through in wafer-to-wafer versus die-to-wafer integration.

Why 0.2 Nanometers Decides the Yield

The reported process window is the most useful part of the story for anyone specifying tools. The dielectric holds on contact through van der Waals forces, so the polished surface can vary by no more than about 0.2 nm. The copper pads must sit a few nanometers below that dielectric plane — recessed enough not to interfere at contact, close enough to swell into contact when the stack is annealed at 200–300 °C. A single particle smaller than a micron holds the surfaces apart and leaves a gap spanning many pads at once.

Nothing in that list is a bonder specification. Coplanarity, copper recess, particle count, and dielectric film quality are all set upstream, in CMP, cleaning, and plasma activation — which is why surface preparation for Cu-Cu hybrid bonding is the stage that actually gates yield, and why the bond mechanism itself is documented in our wafer bonding technologies hub.

Intel's implementation makes the front-end dependency explicit: enabling Foveros Direct on a leading-edge logic node required a dedicated process variant, 18A-PT, which adds the through-silicon vias and bonding support that standard 18A does not carry.

The HBM Deferral: A JEDEC Number, Not a Process Failure

With HBM4 pad pitch at 10 µm, SemiEngineering reporting cited by Tom's Hardware concluded that moving to hybrid bonding at that pitch does not yet make economic sense. SK hynix has planned accordingly — sticking with advanced mass-reflow molded underfill for 16-high HBM4 while keeping hybrid bonding as a backup and continuing to validate 12-high hybrid-bonded samples. The company showed a 16-layer HBM4 sample at CES 2026 built without the all-hybrid bonding many expected the generation to require.

Samsung is pushing from the other side: at GTC in March it claimed hybrid bonding cuts thermal resistance by more than 20% against thermocompression bonding, and its SAINT family includes SAINT-D, which stacks DRAM directly on a logic die. Thermal resistance, warpage, and interconnect fatigue in those stacks are the subject of our 3D packaging reliability guide.

The tool market is not waiting for the products. Analyst tracking cited in the report puts Besi's hybrid-bonding revenue on a path toward roughly €476 million in 2026, up from about €36 million in 2023, with second-half 2025 orders up more than 60% against the first half on early HBM4 production-line bookings. ASMPT has partnered with EV Group; SK hynix is working with Hanwha Semitech on bonders targeting a commercial HBM launch in 2027. Applied Materials holds an equity stake in Besi, and March reports placed Besi at the center of takeover interest from both Lam Research and Applied Materials.

One non-technical drag: Adeia, which holds a large bonding patent portfolio, sued AMD last year alleging that the hybrid bonding behind 3D V-Cache infringes 10 of its patents.

NineScrolls Niche Angle

Read as an equipment story rather than a packaging story, the 2026 snapshot says something specific: the hard requirements in hybrid bonding sit in plasma processing and thin-film deposition, not in the bonder.

Plasma processing. Plasma activation converts the dielectric surface to a hydrophilic, contact-ready state — it is the step that makes room-temperature contact possible at all, and its uniformity is what determines whether the bond front closes cleanly. Separately, the 18A-PT case is a reminder that a hybrid-bonded product carries a TSV module behind it: high-aspect-ratio silicon etch, reveal, and passivation. Labs building toward 3D integration should read surface preparation for Cu-Cu hybrid bonding alongside the deep reactive ion etching and Bosch process guide, since the two modules are specified together.

Thin-film deposition. A 0.2 nm surface-variation budget is a film-uniformity budget before it is a polish budget. The bonding dielectric — SiO₂ or increasingly SiCN — is deposited by PECVD or ALD, and its thickness uniformity, intrinsic stress, and defect density propagate directly into post-bond overlay and void formation. imec's 200 nm pitch with sub-40 nm overlay is as much a deposition result as a bonder result.

Equipment supply chain. The vendor consolidation around bonding tools — Applied Materials' Besi stake, the Lam and Applied takeover interest, ASMPT/EV Group, SK hynix/Hanwha Semitech — is consolidation around integrated platforms that fold surface prep, cleaning, activation, and metrology into the bonder. That raises the value of standalone plasma activation, plasma cleaning, and dielectric deposition capability for university and R&D labs, which need the process steps without the 2,000-chip-per-hour production platform. Research groups working at the 1 µm die-to-wafer regime that CEA-Leti demonstrated need exactly that: controllable ICP-RIE, PECVD, and plasma activation tools, not a high-volume bonder.

The practical read for R&D labs. Hybrid bonding's memory timeline slipping to the end of the decade does not slow the research demand — it extends the window in which pitch, dielectric chemistry, and activation recipes are still open questions. That work happens on flexible process tools.

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