Through-Silicon Vias (TSV): Integration Flows, Design Rules, and Manufacturing Challenges

By NineScrolls Engineering · 2026-06-11 · 14 min read · Process Integration

Every 2.5D and 3D package stands on the same vertical foundation: copper running straight through silicon. The through-silicon via — the TSV — lets signals and power cross a die or interposer in micrometers instead of millimeters, and this guide treats it as exactly that: a packaging element. What a TSV is, when in the flow to make it (via-first, via-middle, or via-last), and how big to design it — those questions belong here. How stacked dies actually join belongs to our Wafer Bonding Technologies Guide, and the application story TSVs made famous — HBM — has its own deep dive. The central argument is simple: where in the flow the via gets made matters more than how any single step works.

1. Why 2.5D/3D Integration Needs TSVs

A through-silicon via is a copper conductor that passes vertically through a thinned silicon die or interposer, electrically connecting the front side to the back side. That single sentence carries the whole value proposition: without a TSV, a signal leaving the top of a die must detour to reach the component below — out to the die edge through wire bonds, or down and across through package substrate traces — a path measured in millimeters. With a TSV, the same signal crosses in the thickness of thinned silicon, typically tens of micrometers. The interconnect shrinks by two to three orders of magnitude, and its resistance, inductance, and capacitance shrink with it.

That shortening is not a refinement; it is what makes modern package architectures possible at all. In 2.5D integration, an interposer routes thousands of connections between chiplets sitting side by side — and TSVs are how those connections, plus the power feeding every chiplet, get from the interposer's routing layers down to the package substrate. In 3D integration, dies stack face-to-back, and TSVs are the vertical bus itself: every signal and every milliamp crossing between stacked dies passes through them. HBM's wide, power-efficient memory interface — thousands of bits in parallel at modest per-pin speed — is only sensible because TSVs make thousands of short vertical connections cheap in power terms; delivered through package-level routing instead, the power budget collapses before the wiring does.

At modern bandwidth and power densities, TSVs are the load-bearing element of the whole 2.5D/3D structure — which is why their geometry deserves the same design attention as the dies they connect.

2. TSV Anatomy and Design Parameters

Structurally, a TSV is a layered cylinder: a via etched through the silicon, lined with a dielectric (typically silicon oxide) for isolation, a thin barrier that keeps copper from diffusing into the silicon, and the copper fill that does the conducting. The via is built blind — the wafer is later thinned from the backside until the copper is exposed for connection. Four parameters define the design.

Diameter. Interposer vias typically run on the order of 10 µm or more, while vias in stacked memory and logic dies push down to a few micrometers. Smaller diameters save silicon area and reduce capacitance, but make every downstream step — lining, filling, revealing — more difficult.

Depth. Depth is set by how thin the die or interposer will ultimately be — typically on the order of 50–100 µm for interposers, considerably less for aggressively stacked dies. Depth and diameter are coupled through the aspect ratio (depth divided by diameter): a 5 µm via through 50 µm of silicon is a 10:1 structure. Designs typically sit around 10:1, and aspect ratio is the single number that most strongly governs how difficult the via is to manufacture.

Pitch. The center-to-center spacing sets how many vertical connections fit in a given area — the whole point of the exercise. The instinct is that pitch scales with diameter: shrink the hole, pack them tighter. It does not, because of the fourth parameter.

Keep-out zone (KOZ). Copper and silicon expand at very different rates with temperature, so a copper-filled via leaves the surrounding silicon under mechanical stress. That stress shifts the electrical behavior of nearby transistors, so design rules forbid active devices within a keep-out zone around each via — an exclusion area extending micrometers beyond the via wall, scaling with via size, process, and device sensitivity. In TSV design, density is rarely limited by the hole diameter alone; it is often limited by the keep-out zone created by stress, layout rules, and device sensitivity. A via occupying a few square micrometers can sterilize many times that area for device placement — which is why KOZ, not diameter, usually decides how many TSVs a floorplan can afford.

TSV anatomy cross-section: oxide liner, barrier layer, copper fill through thinned silicon, with the surrounding keep-out zone annotated — Anatomy of a through-silicon via: dielectric liner for isolation, barrier, and copper core — surrounded by the keep-out zone (KOZ), the stress-driven exclusion area that, more often than the via diameter, sets how densely TSVs can be packed.

3. From Wafer to Stack: The TSV Integration Flow

On paper, building a TSV is a clean sequence. A hard mask or photoresist pattern defines the via openings on the wafer. The vias themselves are then formed, almost universally by deep reactive ion etching — for how the etch achieves these deep, vertical profiles, see our DRIE guide. From there the layered cylinder of Section 2 gets built from the outside in: a dielectric liner is deposited along the via walls to isolate the future conductor from the silicon, followed by a thin diffusion barrier and a copper seed layer that gives electroplating something to grow on. Electroplated copper then fills the via from the bottom up, and an anneal stabilizes the copper's grain structure before any heat-sensitive steps follow. Chemical-mechanical planarization strips the copper overburden back to a flat surface so that normal interconnect processing can continue above the vias.

All of this happens while the via is still blind — a copper-filled well that stops partway through a full-thickness wafer. The via only becomes a through-silicon via at the end: the wafer is mounted to a carrier, thinned from the backside by grinding and etching, and the buried copper is revealed and capped with backside metallization. Only then can the die or interposer be bonded, stacked, and connected into a package.

But the sequence above hides the real decision. It is not how each step works — it is where in the device flow the via gets made. That choice — via-first, via-middle, or via-last — shapes everything downstream.

4. Via-First vs Via-Middle vs Via-Last

Via timing is not a process decision. It is a thermal-budget and ownership decision — who makes the via, and what has already been built when they do.

The three options are named for where the via lands in the device flow, and each one answers the pull-quote's two questions differently.

Via-first puts the vias into the wafer before the transistors exist — before front-end-of-line (FEOL) processing begins. That ordering has one elegant consequence and one severe one. The elegant consequence is alignment: because every later layer is patterned relative to wafers that already contain vias, the devices and interconnect are built around the vias rather than aimed at them, and registration is essentially native. The severe consequence is thermal. A via formed first must survive everything that follows — including front-end steps that run near or above 1000 °C. Copper cannot enter that thermal territory: it would diffuse, deform, and contaminate the front end. So via-first conductors are typically conservative choices such as doped polysilicon, which tolerates the heat but conducts far worse than copper, eroding the electrical advantage that justified the via in the first place. The result is an option commonly described as the least used in mainstream logic and memory flows — viable for specialty devices and certain MEMS-adjacent or power applications, but typically a niche answer rather than a default one. Ownership sits unambiguously with whoever runs the front end, because the via precedes everything they build.

Via-middle forms the via after FEOL but before the back-end-of-line (BEOL) interconnect stack — the transistors exist, the wiring above them does not. This window is the reason via-middle is typically described as the mainstream choice for HBM-class memory and 3D logic stacking. With the front end complete, no remaining step demands extreme temperature, so copper becomes usable and the via inherits copper's low resistance. Because the via is patterned in the fab, on fab-grade lithography, against alignment marks shared with the device layers, registration to the transistors is excellent and the vias can be fine — the few-micrometer, roughly 10:1 geometries of Section 2. And because the step sits inside the device flow, the foundry owns it: the via is a fab process, qualified and yielded like any other fab process, with the foundry carrying responsibility for its interaction with the layers above and below. The cost of that ownership is intrusion — the via interrupts the device flow, and every wafer pays for via processing whether or not the dies are eventually stacked — which is why via-middle tends to appear where stacking is the whole point of the product.

Via-last forms the via after BEOL is complete, often from the back side of the thinned wafer. Historically this is the route CMOS image sensors pioneered, and it remains the option most accessible to OSATs — the outsourced assembly and test houses — because it requires no entry into the device flow at all. The finished wafer arrives intact and protected; nothing about via formation interrupts transistor or interconnect processing, and the foundry's process is untouched. The difficulty moves to the via itself. It must travel through, or land precisely against, a completed stack of devices and wiring, and it must be aligned to features that were patterned long before, from the opposite side of a thinned wafer. Post-stack alignment of that kind is the central problem of via-last, and it pushes the geometry coarse: diameters and pitches are typically larger than via-middle can achieve, and achievable density is correspondingly lower. In exchange, ownership and economics open up — an OSAT can add vias to wafers from any foundry, with no foundry cooperation in the via step.

Choosing among the three is not a matter of weighing pros and cons in the abstract. The decision resolves in a fixed order:

Thermal budget — what high-temperature steps must the via still survive? This eliminates options before preference enters: any front-end heat remaining ahead of the via rules out copper, and usually rules out the timing itself.
Alignment requirement — how precisely must vias land relative to device layers? Fab-grade lithography against shared marks (via-middle) and post-stack alignment from the backside (via-last) are different leagues, and the floorplan's pitch budget decides which league is required.
FEOL/foundry compatibility & ownership — who makes the via: the foundry inside the device flow, or the OSAT after it? Ownership decides supply chain, liability, and cost structure — not just process capability.
Cost & yield risk — the earlier the via, the more subsequent processing its yield multiplies into; a via defect introduced before BEOL forfeits the entire interconnect stack built on top of it.

In practice the order resolves quickly. Thermal budget and ownership rarely leave more than one realistic option on the table, which is why high-bandwidth memory stacks typically land on via-middle and why image sensors, with their packaging-driven requirements and post-fab supply chains, pioneered via-last. The matrix below compresses the whole section into one view.

TSV integration selection matrix comparing via-first, via-middle, and via-last across thermal budget, alignment, foundry ownership, cost, yield risk, and typical use cases, with the four-step decision order — The TSV Integration Selection Framework compares via-first, via-middle, and via-last across the real decision axes: thermal budget, alignment, ownership, cost, and yield risk.

Read the matrix column by column — each timing is a column, each deciding dimension a row — and apply the four-step order from top to bottom: the surviving column is your via timing.

5. TSV Design Rules by Application

The four application classes that dominate TSV deployment are best read as one design space. CMOS image sensors sit at the small, dense extreme — pixel-level interconnect, with vias fine enough to track the pixel array itself. Interposers sit at the large, sparse extreme, where area is cheaper and TSV density matters less than robustness. 3D logic and HBM occupy the middle. The values below are typical ranges and relative tendencies, not specifications.

Application	Diameter	Depth	Aspect ratio	Pitch	KOZ constraint (floorplan impact)
CIS	~1–5 µm class	Follows thinned-die thickness (thinnest of the four)	Moderate to high	Finest	Managed; small in absolute terms
3D Logic	Single-digit µm	Follows thinned-die thickness	Commonly around 10:1	Fine	Most binding floorplan constraint
HBM	~5 µm class	Follows thinned-die thickness (tens of µm)	Commonly around 10:1	Fine to moderate	Grows with via size; budgeted per die
Interposer	~10 µm and up	Follows final interposer thickness	Around 10:1	Coarsest	Largest in absolute terms, least binding (passive silicon)

CIS pioneered fine TSVs because the application demanded it: connecting a pixel array to its readout from the back side, at geometries near the pixel pitch. Vias in the ~1–5 µm class, via-last heritage, the densest packing of the four.

3D logic stacking pushes single-digit-micrometer vias formed via-middle — and it is where the keep-out zone bites first: achievable TSV density is typically set by stress and layout rules, not by how small a hole can be etched.

HBM stacks commonly run thousands of vias in the ~5 µm class through each thinned DRAM die, formed via-middle, with depth following the die thickness. The TSV carries the signal through the silicon; whether the connections between stacked dies are bumps or bonds is its own decision — see our hybrid bonding vs micro-bump comparison.

Interposers carry the largest vias of the four — ~10 µm and up — through the thickest silicon, with depth following the final interposer thickness. Because the silicon is typically passive, the keep-out zone binds less and pitch stays coarse; the design pressure is uniformity and cost across very large die areas.

TSV design rule map: a design-space chart plotting via diameter against pitch and depth for CIS, 3D logic, HBM, and interposer application classes, with keep-out zone tendency annotated — The TSV design-rule map: four application classes arranged from small and dense (CIS) to large and sparse (interposer). Ranges are application-dependent and should be treated as design-space anchors, not universal specifications.

6. What the Packaging Spec Demands of the Etch

From the packaging side, the via-formation step is a black box with a specification sheet attached. The package does not care how the silicon is removed; it cares that the resulting hole meets four kinds of requirements, each driven by a downstream step that fails without it.

Depth and aspect ratio follow from the application class. An interposer that will be thinned to 100 µm needs vias deeper than 100 µm at diameters around 10 µm; an HBM die thinned to 50 µm or below needs a few-micrometer via at aspect ratios near 10:1; a CMOS image sensor stack has its own geometry again. The package architecture fixes these numbers before any wafer is processed, because the final stack height and the floorplan's KOZ budget depend on them.

CD and depth must be uniform across the wafer. Every via on the wafer must land inside the plating and CMP process window: if vias at the wafer edge are shallower or wider than vias at the center, some will underfill or overfill, and a single bad via can strand an entire die. The packaging spec therefore states uniformity as a hard limit, not a preference.

Sidewalls must be smooth and slightly tapered. The dielectric liner and the barrier are thin conformal films that must coat the wall continuously from top to bottom. A rough or reentrant wall starves that coverage — a gap in the liner leaks current into the substrate, and a gap in the barrier lets copper diffuse into the silicon. A gentle positive taper exists to make continuous coverage achievable.

The via bottom must support a clean reveal. After thinning, the copper must emerge at a predictable depth with a profile the backside process can cap reliably; a ragged or uneven bottom turns the reveal into a yield event.

Meeting these numbers is the province of deep-silicon etch engineering — covered in our DRIE guide for how.

7. Manufacturing Challenges and Cost

The economics of TSVs are counterintuitive: the via itself is cheap. Etching millions of holes in parallel costs little per hole. What costs money is the chain the via drags behind it — liner and barrier deposition into deep narrow geometries, copper plating and its anneal, CMP, carrier mounting, wafer thinning, via reveal, backside metallization, and the test steps wrapped around all of it. Cost-per-wafer is dominated by that chain, which is why TSV-based packages tend to make sense only where the bandwidth or form-factor payoff is large.

The defining physical challenge remains copper's thermal expansion. Copper expands several times faster than silicon, so every thermal excursion after fill pushes the copper against its confinement. The visible symptom is copper pumping — the via protruding above the surface after anneal — which threatens any layer built on top. The invisible symptom is the stress field in the surrounding silicon, which is why the keep-out zone of Section 2 exists at all, and why it grows with via size: a larger copper volume stresses a larger region, sterilizing more floorplan area per via. The density argument and the reliability argument are the same argument.

Stacking adds a brutal statistical problem. Dies must be tested and confirmed known-good before stacking, because bonding a good die to a bad one discards both. And the vias themselves compound: a TSV chain is electrically a series circuit, so per-via yield is multiplied across every via in the path. Even very high per-via yield can become unacceptable once multiplied across thousands of vias and stacked interfaces — which is why TSV manufacturing is, above all, an exercise in driving defect densities to levels most fab steps never need to reach.

8. Key Takeaways

A TSV is a packaging entity. Define it by what it is — a copper conductor through thinned silicon — when in the flow it gets made, and how big it must be; the process details belong downstream.
Via timing is settled by thermal budget and ownership. What high-temperature steps remain ahead of the via, and who makes it — foundry or OSAT — typically decide via-first vs via-middle vs via-last before preference enters.
TSV density is more often KOZ-bound than diameter-bound. The stress field around the copper, not the hole size, usually decides how many vias a floorplan can afford.
Design values are design-space anchors. Diameter, depth, aspect ratio, and pitch shift with the application class; treat published ranges as tendencies, not specifications.
A TSV is only one part of the vertical interconnect stack. The next design decisions — TSV reveal, copper filling, and bonding strategy — each deserve their own treatment.

Frequently Asked Questions

What is a TSV?

A through-silicon via (TSV) is a copper conductor that passes vertically through a thinned silicon die or interposer, electrically connecting its front side to its back side. It replaces millimeter-scale package detours with a path tens of micrometers long — the load-bearing vertical interconnect of 2.5D and 3D packages.

What is the difference between via-first, via-middle, and via-last?

The names mark where via formation lands in the device flow. Via-first makes the via before the transistors exist: alignment is native, but the via must survive front-end heat, which rules out copper and leaves it a niche option. Via-middle forms the via after the transistors but before the interconnect stack: copper works, fab-grade alignment enables fine geometry, and the foundry owns the step — commonly the mainstream choice for stacked memory and 3D logic. Via-last adds vias after the wafer is complete: coarser geometry, but accessible to OSATs without entering the device flow.

How dense can TSVs be?

Less dense than the via diameter suggests. TSV density is typically bounded by the keep-out zone — the stress-driven exclusion area around each copper-filled via where active devices cannot be placed — rather than by the hole itself. Floorplans therefore budget vias by KOZ, not by diameter.

Is TSV etching the same as DRIE?

TSV etching is the packaging requirement; DRIE is one common silicon-etching technology used to form high-aspect-ratio vias. This article covers TSV integration and packaging requirements — what the via must look like and when it gets made. For etch mechanisms, process trade-offs, and profile control, see our DRIE guide. The two terms describe different layers of the same problem: the package sets the geometry and the schedule, and the etch technology is judged by how well it delivers them.

NineScrolls supplies deep-silicon etch (ICP) and deposition equipment used in via-formation flows, from research-scale TSV development to pilot production. Specifying a via etch or liner deposition step? Talk to our engineers.