TSV Interposer: The Silicon Routing Layer Between Dies and Package

By NineScrolls Engineering · 2026-06-16 · 9 min read · Process Integration

You have met the through-silicon via as a way to stack chips — to connect one die straight up to the next. A silicon interposer takes the very same structure and points it at the opposite job: instead of building a vertical tower, it spreads chips out side by side and routes them sideways. What the via was, when it is formed, and how an interposer's vias are dimensioned all belong to our parent TSV guide; the memory application that pushes these stacks hardest belongs to our HBM thermal & materials guide; the format choice for joining chiplets belongs to our wafer-to-wafer vs die-to-wafer guide; and the warpage of a large interposer belongs to our 3D packaging reliability hub. This page owns one thing: the same TSV, doing the opposite architectural job.

1. What Is a Silicon Interposer?

A silicon interposer is a thin layer of silicon that sits between the dies and the package substrate — a kind of silicon circuit board. On its top surface it carries a fine redistribution layer (RDL): dense metal routing, patterned at the kind of resolution you reach on silicon rather than on a package, that fans the chips' connections out and links them to one another. Below that routing, punching down through the body of the silicon, are the interposer's own through-silicon vias.

Those vias are what make the interposer more than a passive routing board. The RDL on top is only useful if its signals can reach the package underneath; the silicon body is solid, so the routing has no way down on its own. The interposer's TSVs are that way down — vertical conductors that take each signal from the top-surface routing, through the silicon, to the package below. Strip the vias out and the interposer becomes a routing layer stranded on top of an insulating slab, connected to nothing beneath it.

So the interposer is two things at once: a high-resolution routing surface, and a set of vertical conductors that drop that routing down to the package. The routing spreads connections out across the top; the vias carry them down through the silicon. How those vias are sized and where they sit in the build flow is the parent guide's design-rule map, not this page's — here it is enough that the via is the load-bearing part of the definition.

2. Why 2.5D Needs a Separate Silicon Layer

Place two chiplets next to each other and they have to exchange an enormous number of connections across the gap between them — far more, and at a far finer line-and-space pitch, than an organic package substrate can typically pattern. The substrate hits a density ceiling well below what neighboring chiplets demand, so something with finer routing has to bridge them. Silicon can be patterned at close to on-chip density, so a silicon layer becomes that high-density bridge: the RDL on its surface carries the dense chiplet-to-chiplet traffic the substrate cannot.

But a dense bridge between neighbors is only half the connection. Those chiplets do not only talk to each other — their power, ground, and the signals leaving the package all still have to reach the substrate below. The fine RDL solves the lateral problem and leaves the vertical one untouched: a high-density routing layer with no path down is as stranded here as it was in §1. This is where the interposer's own TSVs come back in. They take that dense surface routing and carry it down through the silicon to the package, so the high-density bridge is also connected to everything beneath it. The silicon layer earns its place by routing sideways at a pitch the substrate cannot — and the vias are what keep that sideways routing from being a dead end.

3. The Interposer's TSVs: A Different Job

In a 3D stack, a die's through-silicon vias point straight up: each via connects one die to the die directly above it, so the structure grows vertically and the vias are the integration — they are the rungs that bind the tower together. The job of the via there is to move a signal from one tier to the next, upward, die onto die.

An interposer uses the same structure for the reverse geometry. Here the chips do not sit on top of one another — they sit side by side on the interposer's top surface and talk horizontally, across the RDL, neighbor to neighbor. The vertical conductor is no longer how chips reach each other; the RDL does that. Instead, the interposer's TSVs take that whole lateral routing layer and carry it down — through the body of the silicon, to the package's C4 bumps on the underside. The via's direction of travel is the same as ever; what changed is what sits at each end of it. In a stack, a via spans the gap between two active dies. In an interposer, it spans the gap between a routing layer above and a package below.

That is the whole inversion. Same vertical copper conductor through silicon, but in a stack it serves vertical integration — chips reaching chips — and in an interposer it serves lateral routing, dropping a sideways-spreading layer down to the package. Remove the via from this picture and there is no interposer left: the routing on top has nowhere to go and the chips are spread out over a slab they cannot connect through. Same structure, opposite job — which is exactly what the next section builds on.

4. Same TSV, Opposite Job: 2.5D vs 3D

You have met the TSV as a way to stack chips. The interposer uses the very same structure to do the opposite — to spread chips out.

Same vertical conductor, opposite architectural job: in 3D the TSV stacks dies upward; in 2.5D the interposer's TSVs carry a lateral routing layer down to the package.

Take the two architectures one at a time. In 3D — vertical stacking — the dies sit on top of one another, and each die's through-silicon vias are the vertical spine threading signal and power straight up through the stack. The integration direction is vertical; the via's job is to connect a die to the one directly above it, so the structure grows tier by tier and the vias are what bind those tiers together. The taller the tower, the more the vias are doing — they are the architecture, not an accessory to it.

In 2.5D — lateral routing — the dies instead sit side by side on the interposer, and they talk horizontally across its surface routing (the RDL), neighbor to neighbor. The interposer's TSVs then take that whole horizontal layer and carry it straight down to the package. The integration direction is lateral — spreading the chips out across the surface — and then down to escape; the via's job here is to connect a routing surface to the package, not a die to a die. The chips reach each other sideways, and the vias are how that sideways layer gets out.

Here is the crux: it is the same through-silicon via — a vertical copper conductor through thinned silicon — doing two opposite jobs, decided entirely by what the silicon it threads happens to be. Thread a die in a stack and the via stacks; thread a routing layer under a row of chips and the via routes. The conductor stayed put; only its surroundings changed — and with them, its role.

Same TSV, opposite job: one through-silicon via forks into vertical stacking in 3D (dies stacked, the TSV the vertical spine) versus lateral routing in 2.5D (dies side-by-side on an interposer whose TSVs carry the routing layer down to the package) — Same TSV, opposite job: a vertical spine that stacks dies in 3D, or a lateral bridge whose vias route a routing layer down to the package in 2.5D.

Read the figure by its direction of travel, not by the packages it draws: follow the via straight up through the stack on one side, and trace it sideways across the routing then down to the package on the other — the same conductor, pointed two opposite ways.

5. Where the Interposer Fits

The interposer appears wherever side-by-side chips must talk faster than a substrate allows — and wherever that lateral traffic still has to reach the package through the interposer's own vias.

High-bandwidth memory beside a logic die. A stack of HBM placed next to a logic die routes its connections across the interposer's surface to that die; the interposer's TSVs then carry the shared lines down to the package. The thermal and materials pressures of those tall memory stacks are covered in our 16-Hi HBM guide.

Chiplet designs across one interposer. Several chiplets can be spread over a single interposer, talking neighbor-to-neighbor through its routing while its vias drop that traffic to the package. How those chiplets are joined is a separate question — see our wafer-to-wafer vs die-to-wafer guide.

CoWoS-style 2.5D. This is the productized form of the pattern: chips sit on a silicon interposer whose surface routes them laterally and whose vias carry that routing down to the package beneath.

6. Why Not Route Directly in the Package?

It is a fair question to press on. A silicon interposer is a large, expensive piece of silicon, and it carries its own through-silicon vias that have to be etched, lined, and filled. If the package already sits underneath, why add a silicon layer at all — why not just route the chips in the package substrate?

The answer is line density. An organic substrate tends to hit a routing-density ceiling, and side-by-side high-bandwidth dies blow straight past it: the number of fine-pitch connections they exchange is more than the substrate can typically pattern. Silicon can be patterned far finer, so the interposer buys a routing pitch the substrate cannot reach — and the vias are how that finer routing escapes the silicon to the package below.

That density comes at a price the industry generally tolerates. There is the added cost of the silicon layer and the vias punched through it — how that cost-chain stacks up is the parent guide's territory, in our TSV guide. There is the reticle-size limit, which caps how large a single interposer can be patterned; designs that need more area tend to be stitched together to exceed it. And there is large-area warpage, which grows with the silicon's footprint — the mechanism behind it belongs to our 3D packaging reliability hub, not this page.

The point underneath all of it: for these workloads the density is usually worth the silicon. And the silicon you pay for is, quite literally, the silicon the vias punch through to reach the package.

7. The Interposer Completes the Picture

The through-silicon via started out, in your reading, as a tool for stacking — a rung between one die and the next. The interposer shows it has a second life. Lay it under a row of side-by-side chips and the same conductor stops being a rung and becomes the routing backbone of a whole 2.5D system: the path by which a dense lateral routing layer escapes downward to the package. One structure, two architectures — vertical in a stack, lateral-then-down in an interposer.

That gives the via three properties worth holding together. It has a depth — how far it is exposed when the wafer is thinned, covered in our TSV reveal guide. It has a fill — which way the copper grows inside it, covered in our TSV copper fill guide. And now it has a role in space — where the chips sit around it. Depth, fill, and placement are three views of the one structure mapped in our TSV guide.

Frequently Asked Questions

What is a silicon interposer?

A silicon interposer is a thin silicon routing layer that sits between side-by-side dies and the package substrate. Its top surface carries dense metal routing that links the chips to one another, and it carries its own through-silicon vias down through the silicon to connect that routing to the package below.

Does an interposer contain active devices?

Most silicon interposers are passive: the silicon carries only the top-surface routing and the through-silicon vias that take it down to the package, with no transistors of its own. An active interposer builds devices into the interposer silicon as well, but the common 2.5D form — chips routed side by side, their traffic carried down through the interposer's vias — uses a passive interposer whose only job is to route.

Why use a silicon interposer instead of the package substrate?

An organic package substrate tends to fall short of the routing density that side-by-side high-bandwidth dies demand — they exchange more fine-pitch connections than it can typically pattern. Silicon can be patterned much finer, so an interposer reaches the density the substrate cannot.

Does an interposer have TSVs?

Yes. An interposer carries its own through-silicon vias, and their job is to take the dense routing on its top surface down to the package — a different job from a 3D stack's die TSVs, which connect one die up to the next. Both are explained in our TSV guide.

Through-Silicon Vias (TSV): The Complete Guide — the parent guide on what the via is and how it is dimensioned.
TSV Reveal — how far the via is exposed when the wafer is thinned.
TSV Copper Fill — which way the copper grows inside the via.
16-Hi HBM: Thermal & Materials Challenges — the memory application that pushes these stacks hardest.
Wafer-to-Wafer vs Die-to-Wafer — how the chiplets on an interposer are assembled.

NineScrolls supplies deep-silicon etch (ICP) systems used to form the interposer through-silicon vias that carry its routing down to the package. Talk to our engineers about your interposer or TSV process.