Deep Reactive Ion Etching (DRIE): Bosch Process Guide for MEMS & TSV

By NineScrolls Engineering · 2025-08-29 · 18 min read · Nanotechnology

1) Introduction to DRIE and the Bosch Process

Deep Reactive Ion Etching (DRIE) is a specialized anisotropic etching technique that enables extremely high aspect ratio (HAR) features in silicon substrates. Unlike conventional Reactive Ion Etching (RIE), which is typically limited to aspect ratios of roughly 5:1, DRIE can achieve vertical sidewalls with aspect ratios exceeding 50:1. This capability makes it indispensable for advanced MEMS, through‑silicon via (TSV) interconnects, and photonic devices.

The Bosch process — named after the patent filed by Franz Laermer and Andrea Schilp at Robert Bosch GmbH in 1994 (U.S. Patent 5,501,893) — has become the dominant DRIE method worldwide. It relies on a rapid, cyclical alternation between a passivation step and an etching step to sculpt vertical silicon structures with excellent precision and repeatability. The technique transformed microfabrication by making features hundreds of micrometers deep practical at production scale.

For foundational context on how DRIE builds upon basic PE and RIE principles, see our PE vs RIE vs ICP-RIE comparison guide.

2) Working Principle of the Bosch Process

The Bosch process achieves its characteristic deep, vertical profiles through a time‑multiplexed alternation of two distinct plasma chemistries. Each cycle consists of a passivation phase followed by an etch phase, repeated hundreds or thousands of times to reach the target depth.

2.1 Passivation Step (C₄F₈)

A fluorocarbon gas — most commonly octafluorocyclobutane (C₄F₈) — is introduced into the chamber. In the plasma, C₄F₈ fragments into CF₂ radicals that polymerize on all exposed surfaces, depositing a thin (typically 10–50 nm) Teflon‑like fluorocarbon film. This conformal polymer coating protects the sidewalls from lateral attack during the subsequent etch step. The deposition rate and thickness are controlled by C₄F₈ flow rate, ICP source power, and step duration.

2.2 Etching Step (SF₆)

Sulfur hexafluoride (SF₆) plasma is then ignited. SF₆ dissociates into highly reactive fluorine radicals (F*) that etch silicon isotropically. However, a substrate bias (RF platen power) accelerates ions vertically toward the wafer surface. This directional ion bombardment preferentially sputters away the passivation polymer at the trench bottom while leaving the sidewall polymer largely intact. The exposed silicon at the bottom is then etched by fluorine radicals, advancing the trench downward. Typical etch rates range from 2–20 μm/min depending on feature geometry and process conditions.

2.3 Cycle Repetition

The two steps alternate rapidly — typically 1–5 seconds each for standard processes, or as short as 0.5 seconds per step for ultra‑smooth sidewall applications. A 100 μm deep trench might require 200–500 cycles. Because each etch step removes a thin layer of silicon at the bottom before re‑passivation, the process yields near‑vertical profiles with excellent anisotropy (sidewall angle > 89°).

Figure 1: Bosch Process Cycle — Step 1 deposits a protective C₄F₈ polymer; Step 2 uses SF₆ plasma with directional ion bombardment to etch the trench bottom; repeated cycling produces deep vertical features with characteristic sidewall scalloping

3) Process Parameters and Control

Achieving optimal DRIE results requires careful tuning of multiple interrelated parameters. The table below summarizes the key variables and their typical operating ranges:

3.1 Ramped and Multi‑Step Recipes

For deep etches (>100 μm), process parameters often need to change as the trench deepens. This is because reactant transport to the trench bottom becomes increasingly difficult with depth. Advanced DRIE tools support ramped recipes where gas flows, pressures, and cycle times are gradually adjusted throughout the process to compensate for depth‑dependent effects. For example, increasing SF₆ flow and chamber pressure at later stages can maintain etch rate uniformity in deep features.

4) Applications of DRIE

The ability to etch deep, high aspect ratio features in silicon with vertical sidewalls has made DRIE essential across numerous technology domains:

4.1 MEMS (Micro‑Electro‑Mechanical Systems)

DRIE is the workhorse of MEMS fabrication. Inertial sensors (gyroscopes, accelerometers), pressure sensors, micro‑mirrors, and resonators all rely on precisely etched silicon structures. Features typically range from 10–500 μm deep with critical dimensions as small as 1–2 μm. The Bosch process enables the release of freestanding mechanical structures by etching through the full wafer thickness (typically 525 μm for a standard 200 mm wafer).

4.2 Through‑Silicon Vias (TSVs)

3D IC integration and advanced packaging technologies such as high bandwidth memory (HBM) and chiplet architectures require electrical connections that pass vertically through silicon. TSVs are typically 5–10 μm in diameter and 50–100 μm deep (via‑middle) or 25–50 μm diameter and 300+ μm deep (via‑last). DRIE provides the necessary depth and profile control, and post‑etch sidewall quality directly affects the conformality of subsequent barrier/seed layer deposition — typically a CVD or HDP-CVD dielectric liner for via isolation. For a side-by-side comparison of DRIE against ion-beam approaches when material chemistry rules out reactive etching, see our RIE vs Ion Milling guide.

4.3 Photonics and Optical Devices

Silicon photonic components — including waveguides, Bragg gratings, and micro‑mirrors — demand smooth, vertical sidewalls for low optical loss. While standard Bosch process scalloping may be too rough for some photonic applications, optimized short‑cycle recipes or cryogenic DRIE can achieve the surface quality needed (Ra < 20 nm).

4.4 Microfluidics

Lab‑on‑chip devices, micro‑reactors, and bioMEMS use DRIE to create high aspect ratio channels, chambers, and nozzle structures. Channel depths of 50–300 μm with widths of 10–50 μm are common. The ability to etch features with well‑controlled sidewall angles enables precise fluidic behavior and reliable bonding to cap wafers.

4.5 Power Electronics

Deep isolation trenches (20–100 μm) in power semiconductor devices provide electrical isolation between high‑voltage and low‑voltage regions. Superjunction MOSFETs and IGBTs use DRIE‑etched trenches that are subsequently filled with oxide or polysilicon to create the charge‑balanced structures necessary for high breakdown voltage.

5) Scallop Control and Common DRIE Defects

Despite its versatility, the Bosch process introduces several characteristic artifacts that engineers must understand and address. Sidewall scalloping is the dominant one and the focus of most process tuning effort.

5.1 Sidewall Scalloping & Cycle-Time Tuning

The most recognizable artifact of the Bosch process is sidewall scalloping — a periodic waviness on the trench walls caused by the alternating etch/passivation cycles. Each etch step isotropically removes a small amount of silicon laterally before the next passivation step re‑protects the surface. Scallop amplitude scales roughly linearly with etch-step duration and inversely with passivation effectiveness. Standard cycle times (2–5 s) produce 50–200 nm scallops; ultra-short cycles (< 1 s) push amplitude under 30 nm at the cost of net etch rate.

Why it matters: scallop roughness degrades thin-film conformality in TSV metallization, increases optical scattering in photonic devices, and reduces fatigue life in MEMS resonators. The table below summarizes the cycle-tuning regimes engineers actually use:

Beyond cycle tuning, the four post-process options to further reduce scallop roughness are:

• Isotropic SF₆ smoothing — A brief bias-off SF₆ pulse after the main etch reduces peak-to-valley by 70–90% but rounds critical dimensions.
• Thermal oxidation + oxide strip — Sacrificial oxidation at 1000 °C followed by HF strip planarizes scallops via differential consumption.
• H₂ anneal — 1000–1100 °C in H₂ drives surface silicon migration that smooths scallops without dimensional loss; standard for premium photonic Si waveguides.
• Switch to cryogenic DRIE — Eliminates scallop formation entirely by replacing the Bosch cycle with continuous SF₆/O₂ at −100 to −120 °C; requires LN₂ infrastructure.

Figure 2: Sidewall Scalloping — Close‑up of periodic sidewall roughness from Bosch cycles, effect of cycle duration on scallop depth, mitigation strategies, and comparison of Bosch (scalloped, Ra 50–200 nm) vs cryogenic DRIE (smooth, Ra < 10 nm)

5.2 Aspect Ratio Dependent Etching (ARDE)

ARDE — also called RIE lag — is the phenomenon where narrow trenches etch more slowly than wide ones under identical process conditions. The root cause is Knudsen transport: as the aspect ratio increases, neutral reactant species (fluorine radicals) have a decreasing probability of reaching the trench bottom due to wall collisions. For aspect ratios above 10:1, etch rate can drop to 50% or less of the open‑area rate, causing significant depth non‑uniformity across features of different widths on the same wafer.

Figure 3: ARDE (RIE Lag) — Wider trenches etch significantly deeper than narrow ones in the same process time. The etch rate vs aspect ratio curve shows exponential roll‑off due to Knudsen diffusion transport limitation of reactive species

Mitigation approaches for ARDE include:

• Pressure ramping — Increasing chamber pressure during deep etching provides more reactant molecules to improve transport into narrow features.
• Dynamic gas flow adjustment — Modulating SF₆/C₄F₈ ratio as depth increases.
• Pulsed bias schemes — Time‑modulated ion bombardment can improve bottom access in high AR features.
• Design rules — Keeping feature widths uniform where possible, or adding dummy features to equalize local loading.

5.3 Notching (Footing) Effect

When etching silicon that sits on an insulating layer (e.g., SOI buried oxide), positive charge accumulates on the exposed dielectric at the trench bottom. This charge deflects incoming ions laterally, causing an undercut "notch" or "foot" at the silicon/oxide interface. Notching can be mitigated with pulsed‑LF bias, which allows charge dissipation between pulses, or by using low‑frequency (380 kHz) substrate bias.

5.4 Grass and Micromasking

Silicon "grass" — needle‑like residues at the trench bottom — occurs when re‑deposited mask material or non‑volatile etch byproducts create micro‑scale etch masks. Contributing factors include poor mask quality, excessive polymer buildup, and inadequate ion bombardment. Prevention involves optimizing the passivation/etch ratio, ensuring sufficient platen power, and using clean mask materials with minimal sputtering.

5.5 Profile Tilting and Bowing

Non‑vertical profiles can result from angular ion distribution effects. Bowing (barrel‑shaped profiles) occurs when ions reflected from the upper sidewalls accelerate lateral etching mid‑trench. Tilting results from asymmetric ion flux, often caused by wafer placement or chamber asymmetry. Both are addressed through careful platen power control, pressure optimization, and chamber maintenance.

6) Future Trends in DRIE

6.1 Cryogenic DRIE

Cryogenic DRIE operates at substrate temperatures of −80 °C to −120 °C using a continuous SF₆/O₂ chemistry (no cycling). At cryogenic temperatures, the oxygen‑silicon passivation layer that forms on sidewalls is stable enough to prevent lateral etching, while the trench bottom is continuously cleared by ion bombardment. The key advantage is scallop‑free sidewalls (Ra < 5 nm), making it attractive for photonic and MEMS applications requiring optical‑quality surfaces. However, cryogenic systems require specialized chuck cooling and the process window is generally narrower than Bosch. For an in‑depth comparison, see our Cryogenic Etching vs. Bosch Process guide.

6.2 Atomic Layer Etching (ALE)

ALE applies the concept of self‑limiting surface reactions to etching, enabling sub‑nanometer depth control per cycle. While ALE is too slow for deep etching, hybrid approaches that combine ALE precision for critical surfaces with conventional DRIE for bulk removal are being developed for applications like FinFET gate etching and advanced 3D NAND structures.

6.3 AI and Machine Learning Process Control

Modern DRIE tools increasingly incorporate real‑time process monitoring (optical emission spectroscopy, laser interferometry) coupled with ML algorithms for endpoint detection, chamber‑to‑chamber matching, and recipe auto‑optimization. These approaches can reduce process development time and improve run‑to‑run repeatability, particularly for high‑mix MEMS fabs.

6.4 Heterogeneous Integration and Advanced Packaging

The semiconductor industry's shift toward chiplet architectures and 3D stacking is driving demand for higher‑density TSVs, deeper vias, and tighter pitch features. DRIE process development is evolving to meet these needs with improved uniformity, throughput, and compatibility with advanced wafer‑level packaging flows.

7) Conclusion & Call‑to‑Action

The Bosch process has fundamentally expanded the capabilities of silicon microfabrication, enabling the miniaturization and integration of MEMS, photonics, power devices, and 3D ICs. Understanding the interplay between process parameters, sidewall quality, and etch uniformity is essential for engineers working with deep silicon etching. As the industry moves toward even more demanding aspect ratios and tighter dimensional tolerances, innovations in cryogenic processes, ALE, and intelligent process control will continue to advance what DRIE can achieve.

Need guidance on Bosch vs cryogenic DRIE for your application? Our engineers at NineScrolls can help evaluate your aspect ratio, etch depth, and material stack to recommend the optimal DRIE solution for your process requirements.

ICP Etcher Series · DRIE Solutions · Contact Us for DRIE Consultation

FAQ

Q1: What is the Bosch process in DRIE?
A: The Bosch process is a time-multiplexed deep reactive ion etch that alternates short SF₆ etch steps with C₄F₈ passivation steps. The fluorocarbon film deposited during passivation protects sidewalls from lateral attack so subsequent etch cycles drive vertically into silicon, enabling aspect ratios well beyond what continuous-mode RIE can deliver.

Q2: How do you control scalloping in DRIE?
A: Scallop amplitude is set primarily by etch step duration and ion energy. Shorter etch cycles (1–3 s instead of 5–8 s), reduced platen bias during the etch step, and higher passivation gas flow shrink scallops to under 50 nm. For sub-20 nm sidewall roughness, pulsed-bias Bosch or cryogenic DRIE is usually a better fit than aggressive cycle-time tuning.

Q3: What is the typical etch rate of Bosch DRIE for silicon?
A: Standard Bosch recipes achieve 3–10 µm/min for silicon, with high-throughput recipes reaching 15–20 µm/min at the cost of slightly larger scallops and reduced selectivity. Etch rate scales with ICP power, SF₆ flow, and chamber pressure, but high-AR features run slower due to ARDE (aspect-ratio-dependent etching).

Q4: Bosch DRIE vs cryogenic DRIE — which should I choose?
A: Choose Bosch when you need batch-friendly room-temperature operation, high throughput, and well-understood recipes for MEMS / TSV. Choose cryogenic DRIE (substrate at -100 to -120 °C) when sidewall smoothness is critical (photonics, optical MEMS) or when aspect ratios exceed 50:1 — cryo eliminates scallops by suppressing lateral etch chemically rather than by passivation cycles. Cryo systems require LN₂ infrastructure and tighter temperature control.

Q5: What are the most common DRIE defects and how do you fix them?
A: The four recurring defects are (1) grass / black silicon from micromasking — fix with longer over-etch and chamber clean; (2) notching at the buried oxide of SOI wafers — switch to pulsed-bias mode; (3) ARDE with narrower features etching slower — compensate via mask CD bias or ramp-up of bias mid-recipe; and (4) excessive sidewall roughness — reduce etch cycle time and increase passivation step.

References

1. Laermer, F. & Schilp, A. "Method of Anisotropically Etching Silicon." U.S. Patent 5,501,893 (1996). Robert Bosch GmbH.
2. Wu, B., Kumar, A. & Pamarthy, S. "High aspect ratio silicon etch: A review." Journal of Applied Physics, 108(5), 051101 (2010). doi:10.1063/1.3474652
3. Blauw, M. A., et al. "Advanced time-multiplexed plasma etching of high aspect ratio silicon structures." Journal of Vacuum Science & Technology B, 20(6), 3106–3110 (2002). doi:10.1116/1.1523403
4. Rangelow, I. W. "Critical tasks in high aspect ratio silicon dry etching for microelectromechanical systems." Journal of Vacuum Science & Technology A, 21(4), 1550–1562 (2003). doi:10.1116/1.1580488
5. Marty, F., et al. "Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures." Microelectronics Journal, 36(7), 673–677 (2005). doi:10.1016/j.mejo.2005.04.039
6. Henry, M. D., et al. "Alumina etch masks for fabrication of high-aspect-ratio silicon micropillars and nanopillars." Nanotechnology, 20(25), 255305 (2009). doi:10.1088/0957-4484/20/25/255305
7. Sammak, A., et al. "Deep reactive ion etching of silicon for microsystem fabrication." Journal of Micromechanics and Microengineering, 16(4), 912–916 (2006).
8. Gerlt, M. S., et al. "Reduced etch lag and high aspect ratios by deep reactive ion etching (DRIE)." Micromachines, 12(5), 542 (2021). doi:10.3390/mi12050542