MEMS Fabrication Process Guide – From Design to Device
By NineScrolls Engineering · 2026-04-15 · 22 min read · Nanotechnology
Target Readers: MEMS process engineers, product engineers, PIs and lab managers building MEMS fabrication capabilities, R&D procurement teams evaluating micro/nanofabrication equipment for MEMS applications. Engineers transitioning from conventional CMOS fabrication to MEMS will find the structural release and movable-part sections especially relevant.
TL;DR Summary
MEMS devices — accelerometers, gyroscopes, pressure sensors, microfluidic chips, RF switches, and optical mirrors — combine mechanical structures with electrical functionality at the micrometer scale. Unlike conventional IC fabrication that builds planar transistors, MEMS requires creating three-dimensional movable structures: cantilevers, membranes, comb drives, and suspended beams. This guide covers the complete MEMS fabrication chain: substrate selection, bulk micromachining (wet and dry), surface micromachining, DRIE (Bosch and cryogenic processes), thin-film deposition (PECVD, LPCVD, sputtering, ALD), wafer bonding, sacrificial layer release, critical point drying, and packaging — with practical process windows, failure modes, and equipment selection criteria for each step.
1) What Makes MEMS Fabrication Unique
MEMS fabrication borrows heavily from semiconductor IC processing — photolithography, thin-film deposition, etching — but introduces fundamental differences that make it a distinct discipline. The core challenge: MEMS devices have moving parts. A pressure sensor needs a suspended membrane that deflects under load. An accelerometer requires a proof mass on compliant springs. An optical MEMS mirror must tilt freely on torsion hinges. Creating these free-standing mechanical structures demands process steps that don't exist in CMOS: deep etching through hundreds of microns of silicon, sacrificial layer release without stiction, hermetic packaging of fragile microstructures, and stress engineering of structural films to prevent curling.
MEMS vs CMOS: Key Fabrication Differences
| Aspect | CMOS IC | MEMS |
|---|---|---|
| Feature depth | < 1 µm (planar) | 10–500 µm (3D structures) |
| Moving parts | None | Cantilevers, membranes, comb drives, hinges |
| Materials | Si, SiO₂, poly-Si, metals | + piezoelectrics (AlN, PZT), SiC, polymers, glass |
| Etch depth | nm–low µm | Tens to hundreds of µm; through-wafer |
| Aspect ratio | Moderate (< 10:1) | Extreme (> 20:1, up to 50:1) |
| Release step | Not applicable | Critical: sacrificial layer removal + anti-stiction |
| Packaging | Hermetic, no mechanical interface | Must accommodate motion, media access (pressure ports), vacuum/gas environment |
| Wafer thickness | Standard (725 µm for 200 mm) | Often thinned, bonded multi-wafer stacks |
Key insight: In CMOS, process development converges on a single standard flow (front-end → back-end → packaging). In MEMS, every device type has a different optimal process flow. An accelerometer, a pressure sensor, and a microfluidic chip may share a fab but share almost no process steps. This makes MEMS fabrication inherently more craft-intensive and equipment-flexible than CMOS.
2) MEMS Device Platforms & Fabrication Requirements
2.1 Inertial Sensors (Accelerometers & Gyroscopes)
Inertial MEMS are the highest-volume MEMS devices, shipping billions of units annually for smartphones, automotive ESC, and IoT. The core structure is a proof mass suspended by folded springs, with capacitive comb-drive sensing.
- Structural material: Single-crystal Si (SOI-based) or thick polysilicon (surface micromachined); typical structural thickness 10–30 µm
- Critical dimensions: Comb finger gaps 1–3 µm, spring widths 2–5 µm, proof mass area 200 × 200 µm² to 1 × 1 mm²
- Key process: DRIE for high-aspect-ratio comb structures (> 20:1); etch uniformity across the device directly determines sensitivity matching between X/Y/Z axes
- Release: HF vapor or BHF wet etch of buried oxide (SOI) or sacrificial PSG/TEOS
- Packaging: Hermetic vacuum or low-pressure N₂ environment; getter material for long-term vacuum maintenance; wafer-level packaging (WLP) preferred for cost
2.2 Pressure Sensors
MEMS pressure sensors use a thin silicon membrane that deflects under differential pressure, with piezoresistive or capacitive readout. Applications span automotive (tire pressure, engine management), medical (blood pressure, ventilators), and industrial process control.
- Membrane formation: Back-side bulk micromachining (KOH/TMAH wet etch or DRIE) to create a precisely controlled membrane thickness (1–20 µm)
- Piezoresistors: Ion-implanted p-type resistors in n-type Si membrane; positioned at maximum stress points (membrane edges)
- Cavity sealing: Anodic bonding (Si–glass) or Si–Si fusion bonding to create sealed reference cavity for absolute pressure sensors
- Critical tolerance: Membrane thickness uniformity ±0.5 µm across wafer — directly determines sensitivity and offset spread
2.3 Microfluidic Devices (Lab-on-a-Chip)
Microfluidic MEMS integrate channels (10–500 µm wide), valves, mixers, and reaction chambers for point-of-care diagnostics, drug delivery, and chemical synthesis. Materials range from silicon and glass to PDMS and thermoplastics.
- Channel fabrication: DRIE in Si (smooth sidewalls critical for optical detection), wet etch in glass (HF-based, isotropic), or soft lithography (PDMS molding from SU-8 master)
- Bonding: Si–glass anodic bonding, glass–glass thermal bonding, or PDMS–glass O₂ plasma bonding
- Surface treatment: Hydrophilic/hydrophobic patterning for capillary flow control; silane SAM coatings; plasma activation
- Integration: On-chip electrodes (Au, Pt) for electrochemical detection; thin-film heaters for PCR thermal cycling
2.4 RF MEMS (Switches, Resonators, Filters)
RF MEMS devices offer superior performance over solid-state switches: lower insertion loss (< 0.2 dB), higher isolation (> 40 dB), and near-zero power consumption. Key structures include capacitive shunt switches, ohmic contact switches, and film bulk acoustic resonators (FBAR).
- Structural materials: Au or Al for switch membranes; AlN or ZnO piezoelectric films for resonators; high-resistivity Si or quartz substrates for low RF loss
- Air gap control: Sacrificial polymer (photoresist, polyimide) or SiO₂; gap height 1–3 µm determines pull-in voltage and capacitance ratio
- Metal deposition: Sputtered or evaporated Au (0.5–2 µm) with Cr/Ti adhesion layer; stress control critical to prevent membrane curling
- Dielectric charging: The dominant reliability failure — trapped charge in the capacitive switch dielectric shifts pull-in voltage over cycling; addressed by dielectric material selection (PECVD SiN vs ALD Al₂O₃) and bipolar actuation schemes
2.5 Optical MEMS (Micromirrors, MOEMS)
Optical MEMS include digital micromirror devices (DMDs), tunable optical filters, variable optical attenuators, and LIDAR scanning mirrors. These devices combine precision mechanical actuation with optical-grade surface quality.
- Mirror surface: Al or Au reflective coating on single-crystal Si platform; surface roughness < 5 nm RMS for visible wavelengths, < 20 nm for IR
- Actuation: Electrostatic (comb-drive or parallel plate), electromagnetic, or piezoelectric; tilt angles ±10–15° typical
- Fabrication approach: SOI-based (device layer = mirror + springs, handle = frame) with DRIE-defined torsion hinges; hinge width 1–5 µm determines resonant frequency and angular range
- Packaging: Optical window bonded to cap wafer; anti-reflective coating on window; hermetic seal to prevent particle contamination on mirror surface
Figure 1: Major MEMS Device Platforms — From left: capacitive accelerometer with comb-drive sensing, piezoresistive pressure sensor membrane, microfluidic channel cross-section, RF MEMS capacitive switch, and electrostatic torsion micromirror. Each platform requires a distinct fabrication flow optimized for its specific mechanical and functional requirements.
3) Core Fabrication Processes for MEMS
3.1 Bulk Micromachining
Bulk micromachining removes material from the substrate itself to create 3D structures — cavities, membranes, through-holes, and mesas. It's the oldest MEMS fabrication approach (dating to the 1960s) and remains essential for pressure sensors, ink-jet nozzles, and microfluidic channels.
Wet Etching (KOH, TMAH, EDP)
Anisotropic wet etchants exploit the crystal-orientation-dependent etch rate of silicon. KOH etches {100} planes ~400× faster than {111} planes, producing characteristic 54.7° sidewalls defined by the intersection of {100} and {111} planes.
| Etchant | Concentration | Temperature | Si {100} Rate | {100}/{111} Selectivity | SiO₂ Selectivity | Advantages |
|---|---|---|---|---|---|---|
| KOH | 30–40 wt% | 70–80 °C | 1–1.5 µm/min | ~400:1 | ~200:1 (SiO₂ mask) | Fast, well-characterized, low cost |
| TMAH | 20–25 wt% | 80–90 °C | 0.5–1 µm/min | ~35:1 | ~5000:1 | CMOS-compatible (no K⁺ contamination); SiN mask compatible |
| EDP | Type S or F | 110 °C | 1.2 µm/min | ~35:1 | ~5000:1 | Excellent p⁺⁺ etch stop; metal compatibility |
Process note: KOH is the workhorse for academic and R&D MEMS fabrication due to its speed and simplicity. However, it is incompatible with CMOS (K⁺ ions are a mobile ion contaminant). For CMOS-MEMS integration, TMAH is the standard replacement — slower but with excellent SiO₂ mask selectivity and no alkali metal contamination.
Dry Bulk Micromachining (DRIE)
Deep Reactive Ion Etching (DRIE) has largely replaced wet etching for applications requiring vertical sidewalls, arbitrary layout geometries (no crystal-plane constraints), and through-wafer etching. The Bosch process — alternating SF₆ etch and C₄F₈ passivation cycles — is the dominant DRIE technique for MEMS.
| Parameter | Bosch Process | Cryogenic DRIE |
|---|---|---|
| Mechanism | Alternating SF₆ etch / C₄F₈ passivation | Continuous SF₆/O₂ at −80 to −120 °C |
| Sidewall profile | Scalloped (50–200 nm peak-to-valley) | Smooth (< 10 nm roughness) |
| Etch rate | 5–20 µm/min (Si) | 3–8 µm/min |
| Aspect ratio | > 30:1 demonstrated | > 20:1 typical |
| Selectivity to SiO₂ | 100–200:1 | 50–100:1 |
| Selectivity to PR | 50–100:1 | 30–50:1 |
| Best for | Through-wafer vias, comb drives, deep trenches | Optical MEMS, smooth waveguides, cryo-compatible materials |
Figure 2: DRIE Bosch Process — Alternating etch (SF₆) and passivation (C₄F₈) cycles create high-aspect-ratio structures in silicon. The characteristic scalloped sidewall morphology (50–200 nm) results from the cyclic nature; scallop depth is reduced by shortening cycle times at the expense of etch rate.
3.2 Surface Micromachining
Surface micromachining builds mechanical structures on top of the substrate using alternating layers of structural and sacrificial thin films. The sacrificial layer is selectively removed at the end to release the structure. This approach enables complex multi-layer devices (e.g., polysilicon comb-drive accelerometers with 3+ structural levels) without deep etching into the substrate.
Typical Surface Micromachining Stack
| Layer | Material | Deposition | Typical Thickness | Function |
|---|---|---|---|---|
| Substrate | Si wafer | — | 525–725 µm | Mechanical support |
| Isolation | SiN (low-stress) | LPCVD | 200–600 nm | Electrical isolation, etch stop |
| Sacrificial 1 | PSG or TEOS SiO₂ | LPCVD / PECVD | 1–2 µm | Defines air gap; removed in HF release |
| Structural 1 | Polysilicon | LPCVD | 1–5 µm | Fixed electrodes, interconnects |
| Sacrificial 2 | PSG or TEOS SiO₂ | LPCVD / PECVD | 1–3 µm | Defines structural gaps |
| Structural 2 | Polysilicon | LPCVD | 2–10 µm | Proof mass, comb fingers, springs |
| Metal | Au, Al, or Ti/TiN | Sputter / evaporation | 200–500 nm | Bond pads, interconnects, reflective coating |
Critical process considerations for surface micromachining:
- Polysilicon stress: As-deposited LPCVD poly-Si has compressive stress that causes buckling. Annealing at 1000–1100 °C for 1–2 hr converts to near-zero or slightly tensile stress. Alternatively, in-situ doped poly at specific deposition temperatures (610–630 °C) can achieve low stress without a separate anneal.
- Step coverage: Conformal coating over the patterned sacrificial layer topography is essential. LPCVD provides excellent conformality; PECVD may be adequate for planar regions but suffers at vertical steps.
- Anchor design: Structural layers connect to the substrate through anchors (etched holes in the sacrificial layer, filled during structural deposition). Anchor size and placement determine mechanical robustness and parasitic capacitance.
- Dimples: Small protrusions patterned into the structural layer to minimize contact area if the structure touches the substrate — a stiction mitigation strategy.
3.3 Thin-Film Deposition for MEMS
MEMS fabrication uses a broader palette of deposited films than CMOS, including structural polysilicon, piezoelectric AlN/PZT, low-stress silicon nitride, thick SiO₂ sacrificial layers, and specialized metals. Film stress and its control across the wafer are often the most critical parameters — more so than in CMOS, because MEMS films must support free-standing mechanical function.
| Film | Method | Thickness Range | Stress (typical) | MEMS Application |
|---|---|---|---|---|
| Poly-Si | LPCVD (SiH₄, 620 °C) | 0.5–10 µm | −300 to +50 MPa (tunable) | Structural layers, piezoresistors |
| Low-stress SiN | LPCVD (SiH₂Cl₂ + NH₃) | 0.1–2 µm | ~100 MPa tensile | Membranes, etch masks, insulation |
| PECVD SiO₂ | PECVD (SiH₄ + N₂O) | 0.5–5 µm | −100 to −300 MPa (compressive) | Sacrificial layer, passivation |
| PECVD SiN | PECVD (SiH₄ + NH₃) | 0.1–3 µm | −200 to +200 MPa (tunable) | Passivation, anti-stiction coating |
| AlN | Reactive sputtering | 0.5–3 µm | −200 to +100 MPa | Piezoelectric actuation/sensing (FBAR, pMUT) |
| Al₂O₃ | ALD (TMA + H₂O) | 5–100 nm | +200 to +400 MPa (tensile) | Etch stop, moisture barrier, anti-stiction |
| Au | Sputter / evaporation | 0.1–2 µm | +50 to +200 MPa (tensile) | RF MEMS contacts, bond pads, mirrors |
| Ti/TiN | Sputter | 20–200 nm | Variable | Adhesion, barrier, electrode |
Stress engineering tip: For PECVD films, stress can be shifted from compressive to tensile by increasing RF frequency (from LF 380 kHz to HF 13.56 MHz), decreasing pressure, or increasing power. Dual-frequency PECVD reactors allow mixed-frequency deposition to target near-zero stress — essential for free-standing membranes and cantilevers. For a complete discussion, see our PECVD Complete Guide.
3.4 Lithography for MEMS
MEMS lithography differs from advanced CMOS in a critical way: features are larger (1–20 µm typical), but resist thickness and topography are far greater. Deep trenches, thick structural layers, and multi-level topography create challenges for resist coating, exposure, and development that are unique to MEMS.
- Thick resist processing: DRIE and electroplating require 5–50 µm resist (AZ 4620, AZ 9260, SU-8, KMPR). Spin coating parameters (500–2000 rpm), soft bake ramp rates, and multi-coat strategies differ fundamentally from sub-micron resist processing. See our Spin Coating & Development Guide for detailed protocols.
- Front-to-back alignment: Bulk micromachining requires patterning both sides of the wafer with µm-level alignment. Dedicated double-sided mask aligners or steppers with infrared alignment capability are essential.
- Topography coating: After DRIE or structural deposition, wafer surfaces may have steps of 10–100+ µm. Spray coating or electrodeposition of resist may replace spin coating for severe topography.
- SU-8 permanent structures: The epoxy-based SU-8 resist can serve as a permanent structural material (microfluidic channels, molds for electroplating, bio-MEMS structures) rather than a sacrificial mask. Aspect ratios > 20:1 are achievable with optimized processing.
3.5 Etching for MEMS Structures
MEMS etching encompasses a wider range of depths, materials, and profile requirements than any other fabrication domain. A single MEMS device may require shallow oxide etching (contact windows), medium-depth poly-Si etching (structural patterning), deep silicon DRIE (through-wafer vias), and isotropic release etching — all within the same process flow.
| Etch Step | Material | Depth | Method | Key Requirement |
|---|---|---|---|---|
| Structural poly-Si | Polysilicon | 1–10 µm | RIE (SF₆/C₄F₈ or Cl₂/HBr) | Vertical sidewalls, controlled over-etch |
| Comb-drive DRIE | Si (SOI device layer) | 10–50 µm | DRIE Bosch | High AR (> 20:1), uniform across features |
| Through-wafer via | Si | 200–725 µm | DRIE Bosch | Profile control through full thickness; notching at BOX |
| Membrane thinning | Si | 500–700 µm (leaving 1–20 µm) | KOH/TMAH or DRIE | Thickness uniformity ±0.5 µm |
| SiO₂ sacrificial | SiO₂ (PSG/TEOS) | 1–5 µm | Wet HF or HF vapor | Complete removal under structures without stiction |
| SiN membrane | SiN | 0.1–2 µm | RIE (CF₄/O₂ or CHF₃) | Selectivity to underlying Si or SiO₂ |
| Metal patterning | Al, Au, Ti, Pt | 0.1–2 µm | IBE/RIBE, lift-off, or wet etch | Pattern fidelity, no re-deposition |
| Piezo film | AlN, PZT | 0.5–3 µm | ICP-RIE (Cl₂/BCl₃/Ar) or wet | Sidewall angle, interface damage |
Figure 3: MEMS Etching Approaches — (a) Anisotropic wet etch (KOH) with crystal-plane-defined 54.7° sidewalls, (b) Bosch DRIE with vertical scalloped sidewalls, (c) Cryogenic DRIE with smooth vertical walls, (d) Isotropic release etch creating undercut cavities beneath structural layers.
3.6 Wafer Bonding
Wafer bonding is essential for MEMS packaging, multi-wafer device stacks, and sealed cavity formation. The choice of bonding method depends on material compatibility, thermal budget, bond strength requirements, and hermeticity needs.
| Bonding Method | Materials | Temperature | Bond Strength | Hermetic | MEMS Application |
|---|---|---|---|---|---|
| Anodic | Si–borosilicate glass | 300–450 °C | > 10 MPa | Yes | Pressure sensors, microfluidics, accelerometer caps |
| Si–Si fusion | Si–Si (hydrophilic) | 800–1100 °C | = bulk Si | Yes | SOI wafer fabrication, sealed cavities |
| Eutectic | Au–Si, Au–Sn, Al–Ge | 280–400 °C | Moderate | Yes | WLP, hermetic MEMS caps |
| Thermocompression | Au–Au, Cu–Cu | 300–400 °C | Moderate–High | Yes | 3D integration, RF MEMS packaging |
| Adhesive | BCB, SU-8, polyimide | 150–300 °C | Low–Moderate | No (semi-hermetic) | Temporary bonding, microfluidics, low-temp integration |
| Glass frit | Si–Si with glass interlayer | 400–450 °C | Moderate | Yes | Automotive sensors, high-volume WLP |
3.7 Release Etching & Anti-Stiction
The release step is often the most critical — and the most failure-prone — step in MEMS fabrication. Removing the sacrificial layer to free the mechanical structure without causing stiction (permanent adhesion of the released structure to the substrate) requires careful process design.
Release Methods
- Wet HF release: Standard for SiO₂ sacrificial layers. Buffered HF (BHF, 5:1 to 10:1 NH₄F:HF) or 49% HF depending on etch rate requirements. Complete removal of oxide under large structures requires extended etch times and etch access holes in the structural layer.
- HF vapor release: Avoids liquid-phase stiction entirely. Anhydrous HF vapor at 30–40 °C with alcohol catalyst selectively removes SiO₂. Slower than wet HF but eliminates the rinse/dry stiction risk. Requires dedicated HF vapor etch chamber.
- XeF₂ isotropic Si etch: Used when silicon itself is the sacrificial material (e.g., releasing structures from a Si substrate). Gas-phase, no liquid involved. Selectivity: > 1000:1 to SiO₂, SiN, metals, photoresist.
Anti-Stiction Strategies
| Strategy | Implementation | Effectiveness | Tradeoff |
|---|---|---|---|
| Critical point drying (CPD) | IPA → liquid CO₂ → supercritical CO₂ → vent | High — eliminates capillary forces | Requires CPD tool; batch process |
| SAM coating | FDTS, OTS, or FOTS vapor deposition | Very high — hydrophobic surface | Coating uniformity; long-term stability |
| Surface roughening | Dimples in structural layer; textured substrate | Moderate — reduces contact area | Design constraint; doesn't prevent all modes |
| HF vapor release | Gas-phase etch avoids liquid | High — no capillary forces during release | Slower; may leave residues without optimization |
| Sublimation drying | Replace rinse liquid with t-butanol → freeze → sublimate | Moderate–High | Less standard; substrate temperature control needed |
Best practice: Combining HF vapor release with post-release SAM coating provides the most robust anti-stiction performance. For wet-released devices, CPD followed by immediate SAM deposition (before any air exposure) is the standard industrial approach.
4) Process Integration: Example Flows
4.1 SOI-Based Capacitive Accelerometer
This process flow is representative of high-volume inertial MEMS fabrication using SOI (Silicon-on-Insulator) wafers. The device-layer silicon becomes the mechanical structure; the buried oxide (BOX) serves as the etch stop and sacrificial layer.
| Step | Process | Details | Critical Parameters |
|---|---|---|---|
| 1 | SOI wafer selection | Device layer: 10–30 µm Si; BOX: 1–2 µm SiO₂; Handle: 400–500 µm | Device layer thickness uniformity ±0.5 µm |
| 2 | Lithography (front side) | Pattern comb fingers, springs, proof mass, anchors | CD control ±0.2 µm for 2 µm gaps |
| 3 | DRIE (Bosch) | Etch through device layer, stop on BOX | Sidewall angle 90° ±0.5°; scallop < 100 nm; no notching at BOX |
| 4 | Metallization | Sputter Al (300 nm) + pattern for bond pads | Step coverage into DRIE features |
| 5 | HF vapor release | Remove BOX under proof mass and springs | Complete release; anchor oxide retention |
| 6 | Anti-stiction coating | FDTS SAM vapor deposition | Contact angle > 110°; monolayer uniformity |
| 7 | Cap wafer bonding | Au–Si eutectic bond at 380 °C in vacuum | Cavity pressure < 1 mbar; bond yield > 99% |
| 8 | Backside thinning + dicing | Grind handle wafer; laser or stealth dicing | No particle generation on released structures |
Figure 4: SOI Accelerometer Process Flow — Eight-step fabrication sequence from SOI wafer selection through DRIE patterning, metallization, HF vapor release, anti-stiction SAM coating, eutectic cap wafer bonding, and backside thinning/dicing.
4.2 Piezoresistive Pressure Sensor
| Step | Process | Details |
|---|---|---|
| 1 | Thermal oxidation | Grow 500 nm SiO₂ on both sides of n-type Si wafer |
| 2 | Piezoresistor implantation | Pattern + boron implant (p-type) on front side; dose and energy set Wheatstone bridge sensitivity |
| 3 | Implant anneal + drive-in | 1000 °C, 30 min in N₂; activates dopants, defines junction depth |
| 4 | Contact window etch | RIE through SiO₂ to reach piezoresistor and substrate contacts |
| 5 | Metallization | Sputter Al-Si (1%, 500 nm), pattern interconnects and bond pads |
| 6 | Backside cavity etch | Pattern backside oxide; KOH etch (80 °C, 30 wt%) with front-side protection; stop at target membrane thickness (10–20 µm) using electrochemical or timed etch stop |
| 7 | Passivation | PECVD SiN (300 nm) on front side for environmental protection |
| 8 | Anodic bonding | Bond Si sensor die to Pyrex glass for absolute pressure reference cavity (380 °C, 800 V) |
5) Equipment Selection for MEMS Fabrication
MEMS fabrication equipment must handle wider process windows, larger feature depths, and more diverse materials than conventional CMOS tools. The table below maps key equipment categories to their MEMS-specific requirements.
5.1 Etching Systems
| Equipment | MEMS Requirement | Key Specifications |
|---|---|---|
| ICP-RIE / DRIE | Through-wafer etching, high-AR structures, Bosch + cryo modes | Etch rate > 10 µm/min; uniformity < ±3% on 150 mm; time-multiplexed gas switching < 1 s |
| RIE | Shallow structural etching, oxide/nitride patterning, descum | Multiple gas capability (SF₆, CF₄, CHF₃, O₂, Cl₂); endpoint detection; low damage |
| IBE/RIBE | Metal and piezoelectric film patterning with no chemical selectivity requirement | Multi-angle tilt stage; Ar/O₂/CHF₃ beam; < 5 nm surface roughness on Au |
5.2 Deposition Systems
| Equipment | MEMS Requirement | Key Specifications |
|---|---|---|
| PECVD | Sacrificial SiO₂, passivation SiN, low-stress films for membranes | Dual-frequency (HF/LF) for stress tuning; thickness uniformity ±2%; rate > 50 nm/min |
| Magnetron Sputtering | Metal films (Al, Au, Ti, Mo), piezoelectric AlN, barrier layers | Reactive mode for AlN (N₂ flow control); stress uniformity; multi-target for stack deposition |
| ALD | Conformal anti-stiction coatings, etch stop layers, high-κ dielectrics | Uniformity on high-AR structures; low temperature (< 300 °C for post-CMOS); Al₂O₃, HfO₂, TiO₂ |
| HDP-CVD | Gap-fill for deep trenches, thick oxide for planarization | Simultaneous dep/etch for void-free fill; high rate for thick films |
5.3 Lithography & Support Equipment
| Equipment | MEMS Requirement | Key Specifications |
|---|---|---|
| Coater/Developer | Thick resist coating (5–50 µm), multi-coat capability, edge bead removal | Programmable spin speed 500–6000 rpm; integrated hotplate with ramp control; backside rinse |
| Striper/Asher | Thick resist removal, post-DRIE polymer strip, SU-8 removal | Downstream O₂ plasma; high power for thick resist; no damage to released structures |
| Plasma Cleaner | Surface activation for bonding, descum, organic contamination removal | O₂ and Ar plasma; uniform treatment; compatible with bonded wafer stacks |
6) Common Failure Modes & Troubleshooting
| Failure Mode | Root Cause | Diagnosis | Solution |
|---|---|---|---|
| Stiction after release | Capillary forces during wet rinse/dry pull structures to substrate | SEM: structures touching substrate; optical: Newton's rings on membrane | Switch to CPD or HF vapor release; add SAM coating; increase standoff (dimples) |
| Curled cantilevers/membranes | Stress gradient through structural film thickness | Profilometry of released structures; wafer bow before release | Anneal structural poly-Si; adjust PECVD LF/HF power ratio; optimize deposition temperature |
| DRIE notching at BOX | Charge accumulation on insulating BOX deflects ions laterally | SEM cross-section: lateral undercut at Si/SiO₂ interface | Reduce platen power in final cycles; use pulsed bias; apply backside He cooling |
| DRIE ARDE (lag) | Aspect-ratio-dependent etch rate: narrow features etch slower | SEM: depth variation between wide and narrow features | Adjust Bosch cycle parameters; increase pressure; use compensation mask design |
| Incomplete release | Sacrificial oxide not fully removed under large structures | Electrical test: short between structural layer and substrate; optical: residual oxide visible | Add etch access holes in structural layer (2–5 µm diameter, 10–20 µm pitch); increase etch time; use higher HF concentration |
| Wafer bond voids | Particles, surface roughness, incomplete surface activation | IR transmission imaging; SAM (scanning acoustic microscopy) | Improve surface prep (RCA clean + plasma activation); reduce particle count; optimize bonding pressure/temperature profile |
| Thick resist cracking | Thermal stress during rapid soft bake or hard bake | Optical microscopy: radial cracks from wafer edge | Slow bake ramp (2–5 °C/min); use relaxation steps; reduce final bake temperature |
| Piezoelectric film poor c-axis orientation | Substrate surface roughness, contamination, or incorrect seed layer | XRD rocking curve FWHM > 3° for AlN | Improve substrate polish; use Mo or Pt seed layer; optimize sputtering pressure and substrate temperature |
7) Emerging Trends in MEMS Fabrication
7.1 Piezoelectric MEMS (pMUT, PMUT Arrays)
Piezoelectric micromachined ultrasonic transducers (pMUTs) are replacing bulk piezo elements in fingerprint sensors, gesture recognition, and medical imaging. Fabrication requires high-quality c-axis-oriented AlN or ScAlN films (which offer 5× higher piezoelectric coefficient than pure AlN) deposited by reactive sputtering on Mo/Si substrates, followed by careful patterning and cavity formation.
7.2 CMOS-MEMS Monolithic Integration
Integrating MEMS and CMOS on the same die reduces parasitic capacitance and package size. The key constraint: all MEMS processing must stay below ~400 °C to avoid damaging CMOS metallization (Al) and contacts. This drives adoption of PECVD (vs LPCVD), ALD, and low-temperature bonding techniques (eutectic, adhesive).
7.3 Wafer-Level Packaging (WLP)
WLP bonds a cap wafer to the device wafer before dicing, encapsulating MEMS structures at wafer scale. This dramatically reduces packaging cost (the dominant cost component for mature MEMS products) and enables hermetic vacuum environments for inertial sensors. Getter films (Ti, Zr-based alloys) deposited inside the cap cavity maintain vacuum over the device lifetime (> 10 years).
7.4 3D-Printed and Hybrid MEMS
Two-photon polymerization (Nanoscribe) and micro-stereolithography enable rapid prototyping of polymer MEMS structures with sub-micron features. While not yet production-ready for high-volume, these techniques accelerate R&D cycles for microfluidic devices, metamaterial structures, and bio-MEMS scaffolds.
7.5 Advanced Materials
- SiC MEMS: For harsh environments (> 600 °C, corrosive media); pressure sensors for jet engines, deep-well drilling
- Diamond MEMS: Highest Young's modulus and thermal conductivity; NCD/UNCD films for high-Q resonators
- Graphene MEMS: Atomically thin membranes for ultimate pressure sensitivity; suspended graphene resonators with Q > 10,000
- Flexible MEMS: Polymer substrates (PI, PET) with thin-film sensors for wearable and implantable applications
8) Practical Recommendations
For Labs Starting MEMS Fabrication
- Start with SOI. SOI wafers eliminate the need for complex sacrificial layer deposition and stress management. The device layer is single-crystal Si (no stress issues), and the BOX provides a natural etch stop and sacrificial layer. Most academic MEMS labs begin with SOI-based processes.
- Invest in DRIE first. DRIE (ICP-RIE with Bosch capability) is the single most enabling tool for MEMS. It handles comb-drive fabrication, through-wafer vias, membrane thinning, and trench isolation — covering more MEMS process steps than any other single tool.
- Establish a robust release process. Stiction is the #1 yield killer in MEMS. Set up either CPD or HF vapor release capabilities before attempting device fabrication. Budget for SAM coating equipment (vapor-phase deposition).
- Design for process. MEMS layout rules differ from CMOS: include etch access holes in large suspended areas, add dimples at potential stiction points, use symmetric spring designs to cancel stress gradients, and provide sacrificial-etch test structures alongside devices.
- Characterize films early. Before any device fabrication, characterize stress (wafer bow), thickness uniformity, and etch rate of every deposited film. Small stress variations (±50 MPa) that are invisible in CMOS can be catastrophic for MEMS cantilevers.
Equipment Priority Checklist
| Priority | Equipment | MEMS Criticality | Rationale |
|---|---|---|---|
| 1 | ICP-RIE / DRIE | Essential | Core process: comb drives, membranes, vias, trenches |
| 2 | PECVD | Essential | Sacrificial oxide, passivation nitride, stress-tuned membranes |
| 3 | Coater/Developer | Essential | Thick resist processing for DRIE; multi-layer litho |
| 4 | RIE | Essential | Oxide/nitride patterning, descum, thin-film structural etch |
| 5 | Sputtering System | High | Metal deposition, piezoelectric AlN, multi-layer stacks |
| 6 | Striper/Asher | High | Thick resist strip, post-DRIE polymer removal |
| 7 | ALD | Moderate | Conformal anti-stiction coating, etch stops for advanced devices |
| 8 | IBE/RIBE | Moderate | Metal/piezo patterning for RF MEMS, FBAR |
| 9 | Plasma Cleaner | Moderate | Surface activation for bonding, pre-deposition clean |
| 10 | HDP-CVD | Specialized | Void-free gap fill for advanced trench isolation |
Further Reading
- Deep Reactive Ion Etching (DRIE) – The Bosch Process Explained
- Cryogenic Plasma Etching vs. Bosch Process
- Reactive Ion Etching (RIE) – Principles, Applications, and Equipment Guide
- PECVD Complete Guide — Plasma-Enhanced Chemical Vapor Deposition
- Atomic Layer Deposition (ALD) – Comprehensive Guide
- Magnetron Sputtering – Principles and Equipment Guide
- Spin Coating & Development Guide
- Lithography Process Integration Guide
- Ion Beam Etching (IBE) & RIBE Guide
- Plasma Stripping & Ashing Guide