III‑V Compound Semiconductor Etching – Gas Chemistry, Process Windows, and Equipment Guide
By NineScrolls Engineering · 2026-04-15 · 24 min read · Materials Science
Target Readers: Process engineers developing III-V device fabrication, photonics and RF device engineers, compound semiconductor researchers, equipment engineers selecting etch platforms for III-V materials, and procurement teams evaluating ICP-RIE systems for compound semiconductor applications.
TL;DR Summary
III-V compound semiconductors — GaAs, InP, GaN, AlGaN/GaN heterostructures, InGaAs, and antimonides — are the backbone of photonics, RF power amplifiers, high-electron-mobility transistors (HEMTs), laser diodes, and emerging quantum devices. Unlike silicon, III-V etching must contend with multi-element stoichiometry (different volatilities for group-III and group-V etch products), crystallographic damage sensitivity, and the need to preserve delicate heterointerfaces. This guide provides material-by-material gas chemistry recipes, etch rate data, selectivity strategies, damage characterization methods, and equipment selection criteria — the practical knowledge needed to develop production-quality III-V etch processes.
1) Why III-V Etching Is Different from Silicon
Silicon etching is conceptually straightforward: F-based or Cl-based chemistries produce volatile SiF₄ or SiCl₄, and the process engineer's job is controlling the profile. III-V etching is fundamentally more complex because each compound contains two (or more) elements with different etch product volatilities, and the etch must remove both at comparable rates to maintain stoichiometric surfaces.
Key Challenges
| Challenge | Silicon | III-V Compounds |
|---|---|---|
| Etch product volatility | SiF₄, SiCl₄ — both highly volatile | Group-III chlorides (InCl₃: low volatility; GaCl₃: moderate) vs Group-V chlorides (AsCl₃, PCl₃: highly volatile) — mismatch causes non-stoichiometric surfaces |
| Stoichiometry | Single element — not an issue | Preferential removal of group-V leaves group-III-rich surface → increased roughness, electrical damage |
| Crystallographic damage | Tolerant of moderate ion damage | Ion bombardment creates deep-level traps (EL2 in GaAs, nitrogen vacancies in GaN) → degraded device performance |
| Selectivity | Si/SiO₂ selectivity well-established | III-V/III-V selectivity (e.g., GaAs/AlGaAs, InGaAs/InP) requires precise chemistry tuning due to similar bond energies |
| Surface quality | Roughness tolerable for most devices | Photonic devices require < 3 nm RMS; laser facets need atomic smoothness |
| Temperature sensitivity | Broad process window | Many III-V etch products (InCl₃) require elevated substrate temperature (> 150 °C) for volatilization |
Key principle: In III-V etching, the fundamental tradeoff is between etch rate (higher ion energy → faster removal) and surface/subsurface damage (higher ion energy → more lattice displacement). The entire art of III-V process development is navigating this tradeoff for each specific material system and device requirement.
2) Material Systems & Their Etch Chemistry
2.1 GaAs and AlGaAs
GaAs remains the workhorse III-V material for RF devices (pHEMTs, HBTs), infrared detectors, and solar cells. AlxGa1-xAs (x = 0.15–0.45) serves as barrier and cladding layers in GaAs-based heterostructures.
| Chemistry | Gases | GaAs Etch Rate | Profile | Surface Quality | Best For |
|---|---|---|---|---|---|
| Cl₂/BCl₃ | Cl₂ (10–30 sccm) + BCl₃ (5–15 sccm) | 200–800 nm/min | Anisotropic, vertical | Moderate (3–10 nm RMS) | Mesa isolation, via etching, general patterning |
| Cl₂/Ar | Cl₂ (15–25 sccm) + Ar (5–15 sccm) | 150–500 nm/min | Anisotropic | Moderate | Standard mesa etch; Ar enhances physical component |
| SiCl₄/Ar | SiCl₄ (10–20 sccm) + Ar (10–20 sccm) | 100–300 nm/min | Highly anisotropic | Good (< 5 nm RMS) | Smooth sidewalls for ridge waveguide lasers |
| CH₄/H₂/Ar | CH₄ (5–15 sccm) + H₂ (15–30 sccm) + Ar (5–10 sccm) | 30–100 nm/min | Anisotropic, smooth | Excellent (< 2 nm RMS) | Photonic devices, laser facets, low-damage applications |
| BCl₃/N₂ | BCl₃ (15–25 sccm) + N₂ (5–10 sccm) | 100–250 nm/min | Anisotropic | Good | Selective GaAs over AlGaAs (N₂ passivates Al) |
GaAs/AlGaAs selectivity: Achieving high selectivity between GaAs and AlGaAs is critical for HEMT gate recess and laser cladding etch-stop applications. BCl₃-based chemistries provide natural selectivity because Al forms non-volatile Al₂O₃ under Cl₂-lean conditions. Adding N₂ or reducing Cl₂ flow increases selectivity to > 30:1 (GaAs:AlGaAs) at the expense of etch rate. For the highest selectivity (> 100:1), digital etching or citric acid/H₂O₂ wet etch may be used as a final step.
Figure 1: III-V Etch Gas Chemistry Map — Chlorine-based chemistries dominate for GaAs and GaN, while CH₄/H₂ is preferred for InP and low-damage photonic applications. Etch product volatility (especially InCl₃) drives the need for elevated substrate temperatures in In-containing compounds.
2.2 InP and InGaAs
InP and lattice-matched In0.53Ga0.47As are the foundation of 1.3/1.55 µm telecom lasers, photodetectors, and high-speed HBTs. InP etching presents unique challenges due to the low volatility of InCl₃ (boiling point 586 °C) compared to GaCl₃ (201 °C).
| Chemistry | Gases | InP Etch Rate | Substrate Temp | Notes |
|---|---|---|---|---|
| CH₄/H₂/Ar | CH₄ (8–15 sccm) + H₂ (20–40 sccm) + Ar (5–10 sccm) | 50–150 nm/min | 20–60 °C | Gold standard for InP photonics; smooth sidewalls; polymer deposition requires periodic O₂ clean |
| Cl₂/CH₄/H₂ | Cl₂ (5–10 sccm) + CH₄ (5 sccm) + H₂ (20 sccm) | 100–300 nm/min | 150–200 °C | Higher rate than pure CH₄/H₂; requires heated chuck for InCl₃ volatilization |
| Cl₂/Ar (heated) | Cl₂ (15–25 sccm) + Ar (10–15 sccm) | 200–600 nm/min | 180–250 °C | Fast etch rate; requires heated substrate stage; rougher surface than CH₄/H₂ |
| Cl₂/N₂ | Cl₂ (10–20 sccm) + N₂ (5–15 sccm) | 150–400 nm/min | 200 °C | N₂ addition improves sidewall smoothness; good for deep mesa etching |
Process note: The CH₄/H₂ chemistry for InP forms volatile (CH₃)₃In (trimethylindium) and PH₃ as etch products, both volatile at room temperature. This avoids the InCl₃ volatility problem entirely but produces polymer deposition on chamber walls and mask surfaces. A cyclic etch/clean approach (etch in CH₄/H₂, clean in O₂) is standard practice. Polymer buildup on the mask can also be controlled by adding a small O₂ flow (1–3 sccm) during etching.
2.3 GaN and AlGaN (Wide Bandgap)
GaN and AlGaN/GaN heterostructures power RF electronics (5G base stations, radar), power converters (EV inverters, data center supplies), and UV/blue LEDs. GaN is extremely chemically stable — its bond energy (8.92 eV/atom) is nearly 3× that of GaAs (3.4 eV/atom) — making it the most challenging III-V material to etch with conventional chemistries.
| Chemistry | Gases | GaN Etch Rate | Profile | Application |
|---|---|---|---|---|
| Cl₂/BCl₃ | Cl₂ (15–30 sccm) + BCl₃ (10–20 sccm) | 200–600 nm/min | Anisotropic, smooth | Standard GaN mesa isolation, via etching |
| Cl₂/BCl₃/Ar | Cl₂ (20 sccm) + BCl₃ (10 sccm) + Ar (5 sccm) | 300–800 nm/min | Highly anisotropic | Deep mesa, through-GaN vias for vertical devices |
| Cl₂/Ar | Cl₂ (20–30 sccm) + Ar (10–20 sccm) | 150–400 nm/min | Anisotropic | General patterning; higher Ar increases physical component |
| BCl₃/SF₆ | BCl₃ (20 sccm) + SF₆ (5–10 sccm) | 100–250 nm/min | Moderate anisotropy | Selective GaN over AlGaN for gate recess (selectivity 5–20:1) |
| Cl₂/BCl₃/N₂ | Cl₂ (15 sccm) + BCl₃ (10 sccm) + N₂ (5 sccm) | 150–350 nm/min | Smooth sidewalls | LED mesa; N₂ reduces sidewall roughness for light extraction |
GaN gate recess — the critical etch: In AlGaN/GaN HEMTs, the gate recess etch must remove the GaN cap and precisely stop in or on the AlGaN barrier layer (typically 15–25 nm Al0.25Ga0.75N). Over-etching by even 2–3 nm degrades 2DEG density and threshold voltage. Approaches include: (1) low-power ICP-RIE with digital/ALE-like cycling, (2) BCl₃/SF₆ chemistry exploiting AlF formation as an etch-stop, and (3) oxidation-based digital etching (O₂ plasma → HCl dip cycles removing ~1 nm/cycle).
Figure 2: GaN HEMT Gate Recess Etch — The gate recess must precisely stop in/on the thin AlGaN barrier (15–25 nm) to control threshold voltage. Over-etching degrades the 2DEG; under-etching produces normally-on operation. Digital etching (O₂ oxidation + HCl strip) achieves ~1 nm/cycle precision.
2.4 GaSb and InAs/GaSb (Antimonides)
Antimonide-based III-V materials (GaSb, InAs/GaSb type-II superlattices) serve infrared detectors (MWIR/LWIR), thermophotovoltaics, and tunnel FETs. Etching antimonides is complicated by the extremely low volatility of antimony chlorides (SbCl₃ boiling point 223 °C, but SbCl₅ decomposes).
- Cl₂/Ar (heated): Standard approach; substrate temperature 150–200 °C required for SbCl₃ desorption; etch rate 100–300 nm/min
- CH₄/H₂/Ar: Low-damage alternative producing volatile (CH₃)₃Sb; slower (30–80 nm/min) but better surface stoichiometry
- BCl₃/Ar: BCl₃ provides both Cl radicals and physical sputtering; moderate rate at room temperature due to BCl₃ ion-assisted desorption of SbClx
2.5 Ternary and Quaternary Alloys
Multi-component alloys (InGaAs, InGaAsP, AlInGaP, InAlAs) present compounded challenges — each element has different etch product volatility, and composition-dependent etch rates cause differential etching in graded layers.
| Alloy System | Preferred Chemistry | Critical Issue | Device Application |
|---|---|---|---|
| InxGa1-xAs | CH₄/H₂/Ar or Cl₂/CH₄/H₂ | In-rich surface at high x; CH₄/H₂ preferred for x > 0.5 | Telecom photodetectors, HBTs, QW lasers |
| InGaAsP | CH₄/H₂/Ar | Four-element stoichiometry; slow etch rate (20–60 nm/min) | Telecom laser active regions, waveguides |
| AlInGaP | Cl₂/BCl₃/Ar | Al content forms passivating oxide; BCl₃ assists Al removal | Visible LEDs (red/orange/yellow), solar cells |
| InAlAs | Cl₂/BCl₃ (heated) or CH₄/H₂ | Both In and Al etch products have low volatility at RT | Metamorphic HEMTs, barrier layers |
3) Etch Mechanisms & Process Control
3.1 Ion-Assisted Chemical Etching
Nearly all III-V dry etching relies on the synergy between chemical reactions and ion bombardment. Pure chemical etching of most III-V compounds is negligibly slow at room temperature (GaN is essentially inert to Cl₂ without ion assistance). The ion bombardment serves three functions:
- Bond breaking: Displaces surface atoms, creating dangling bonds for chemical attack
- Product desorption: Provides kinetic energy to eject low-volatility etch products (InCl₃, AlCl₃) from the surface
- Passivation removal: Sputters away passivation layers (native oxide, polymer deposits) that block chemical etching
The ICP-RIE configuration is ideal for III-V etching because it decouples plasma density (ICP power → radical/ion density) from ion energy (platen/bias power → ion bombardment energy). This allows high etch rates with controlled damage — a critical requirement for III-V devices.
3.2 Process Parameter Effects
| Parameter | Increase Effect | III-V Specific Consideration |
|---|---|---|
| ICP power | ↑ Radical density → ↑ etch rate; ↑ ion density | Higher ICP can improve stoichiometry by providing more reactive species; but excessive ICP power increases ion flux → more lattice damage |
| Platen (RF bias) power | ↑ Ion energy → ↑ etch rate, ↑ anisotropy | Most sensitive parameter for III-V damage; keep DC self-bias < 100 V for low-damage applications; < 200 V for general patterning |
| Pressure | ↑ Pressure → ↑ chemical component, ↓ ion energy (more collisions) | Higher pressure (10–30 mTorr) favors smoother surfaces but may reduce anisotropy; lower pressure (2–5 mTorr) gives more directional etch |
| Substrate temperature | ↑ Temperature → ↑ etch product desorption | Critical for In-containing materials (InP, InGaAs): < 100 °C → InCl₃ accumulates on surface; > 150 °C → adequate volatilization; > 250 °C → risk of thermal decomposition of some III-V surfaces |
| Cl₂:BCl₃ ratio | ↑ Cl₂ → more reactive (faster etch); ↑ BCl₃ → more physical + native oxide removal | BCl₃ is essential for removing native oxides on Al-containing compounds; also reduces water vapor effects in the chamber |
| Gas flow rate | ↑ Flow → ↑ fresh reactant supply, ↓ residence time | Affects etch product clearance; higher flow helps prevent redeposition of non-volatile products |
3.3 Etch Damage & Characterization
Ion bombardment during III-V etching creates subsurface damage extending 10–100 nm below the etched surface, depending on ion energy. This damage directly affects device performance:
| Damage Type | Mechanism | Device Impact | Characterization Method |
|---|---|---|---|
| Point defects | Ion-displaced atoms create vacancies and interstitials | Carrier trapping, increased leakage, reduced minority carrier lifetime | DLTS (deep-level transient spectroscopy), PL intensity |
| Preferential sputtering | Lighter group-V atoms sputtered faster → group-III-rich surface | Surface Fermi level pinning, non-ohmic contacts, increased surface recombination | XPS (composition), AFM (roughness) |
| Amorphization | Severe ion bombardment disrupts crystal structure | Complete loss of semiconductor properties in damaged region | TEM cross-section, RHEED |
| Passivation implantation | N, H, or Cl implanted into subsurface during etching | Compensation doping, reduced carrier concentration | SIMS (impurity profiling), Hall measurements |
Damage recovery strategies:
- Post-etch anneal: RTA at 400–600 °C in N₂ or forming gas (N₂/H₂) can recover 50–80% of point defect damage in GaAs and InP; higher temperatures risk surface decomposition
- Wet chemical treatment: Dilute HCl or citric acid dip removes the damaged surface layer (5–20 nm); effective for contact improvement
- Digital etching finish: After bulk ICP-RIE removal, use gentle digital etch cycles (oxidize + strip) to remove the ion-damaged layer with atomic-level control
- (NH₄)₂S passivation: Sulfide treatment replaces surface oxides and dangling bonds with S bonds; reduces surface recombination velocity by 10–100×
Figure 3: Etch Damage Depth Profiles — Subsurface damage extends 50–100 nm under high-bias conditions, 10–30 nm under optimized low-bias ICP-RIE, and < 5 nm with digital etching. The damaged region contains point defects, implanted species, and non-stoichiometric composition.
4) Application-Specific Process Integration
4.1 InP-Based Photonic Integrated Circuits (PICs)
InP PICs integrate lasers, modulators, photodetectors, and waveguides on a single chip for telecom and data center interconnects. Etch requirements are among the most demanding in III-V processing:
- Ridge waveguide: 1.5–3 µm deep etch in InP/InGaAsP with sidewall roughness < 3 nm RMS and sidewall angle 88–90° for low optical loss (< 1 dB/cm)
- Deep etch (deeply etched ridge): 4–6 µm through the active region for tight optical confinement; requires excellent mask selectivity (SiO₂ or Ni hard mask)
- Selective layer removal: InGaAs contact layer over InP cladding; InP stop-etch layers in quaternary structures
Typical process flow: PECVD SiO₂ hard mask (400 nm) → EBL or DUV lithography → CHF₃/Ar RIE of SiO₂ → ICP-RIE in CH₄/H₂/Ar (main etch) → periodic O₂ plasma clean (every 500 nm depth) → HCl:H₃PO₄ damage removal dip → (NH₄)₂S passivation → PECVD SiN encapsulation.
4.2 GaN Power Device Fabrication
GaN-on-Si power devices (650 V–1200 V) require multiple etch steps with different depth and damage requirements:
| Etch Step | Depth | Chemistry | Key Requirement |
|---|---|---|---|
| Mesa isolation | 200–500 nm | Cl₂/BCl₃ ICP-RIE | Through 2DEG into buffer; moderate damage acceptable |
| Gate recess (E-mode) | 10–25 nm (into AlGaN) | Digital etch or low-power Cl₂/BCl₃ | Atomic-level depth control; minimal damage to 2DEG interface |
| Ohmic contact recess | 20–30 nm | BCl₃/Cl₂ ICP-RIE | Access to 2DEG for low contact resistance (< 0.3 Ω·mm) |
| Through-GaN via | 2–5 µm | Cl₂/BCl₃/Ar ICP-RIE | Vertical profile; high rate; ground plane connection |
| Through-Si via (backside) | 100–200 µm | SF₆/C₄F₈ Bosch DRIE | Standard Si DRIE; stop on GaN buffer (AlN nucleation layer) |
4.3 VCSEL and Edge-Emitting Laser Fabrication
Vertical-cavity surface-emitting lasers (VCSELs) for 3D sensing and data communications require precise mesa etching through AlGaAs/GaAs DBR mirrors (20–40 pairs, total depth 4–6 µm) with smooth sidewalls for current confinement:
- Mesa etch: SiCl₄/Ar ICP-RIE for smooth sidewalls; etch depth monitored in-situ by laser reflectometry to stop at specific DBR period
- Oxidation access: Partial mesa etch to expose high-Al AlGaAs layer for selective wet oxidation (oxide aperture defines current confinement)
- Sidewall passivation: Post-etch BCB planarization or PECVD SiN for surface state reduction and current leakage prevention
Figure 4: III-V Device Applications Requiring Precision Etching — (a) InP-based photonic integrated circuit with ridge waveguides, (b) AlGaN/GaN HEMT with gate recess, (c) GaAs VCSEL with DBR mesa, (d) InAs/GaSb superlattice infrared detector pixel. Each application demands specific etch depth, profile, damage, and selectivity control.
5) Equipment Selection for III-V Etching
5.1 ICP-RIE System Requirements
ICP-RIE is the primary etch platform for III-V compounds. Key specifications for III-V processing differ significantly from silicon-focused systems:
| Feature | III-V Requirement | Rationale |
|---|---|---|
| Substrate heating | Room temperature to 300 °C programmable | Essential for In-containing and Sb-containing compounds; InCl₃ requires > 150 °C for volatilization |
| Low-bias capability | DC self-bias controllable 10–300 V | Low-damage etching of photonic and quantum devices requires < 50 V bias; general patterning uses 100–200 V |
| Gas panel | Cl₂, BCl₃, CH₄, H₂, Ar, N₂, O₂, SF₆ (minimum) | Different material systems require different chemistries; CH₄/H₂ for InP, Cl₂/BCl₃ for GaN, BCl₃/SF₆ for selective GaN/AlGaN |
| Chamber material | Alumina or quartz liner; avoid Al chamber with Cl₂ chemistry | Chlorine-based chemistries attack aluminum; chamber corrosion creates particles and Al contamination |
| Endpoint detection | Laser interferometry or OES | Critical for heterostructure etch stops (e.g., GaAs/AlGaAs, InGaAs/InP); OES monitors specific emission lines (Ga 417 nm, In 451 nm, N 674 nm) |
| Load-lock | Required | Prevents chamber exposure to moisture; reduces native oxide on III-V surfaces; critical for process reproducibility |
| Pressure range | 1–50 mTorr | Low pressure (2–5 mTorr) for anisotropic etching; higher pressure (10–30 mTorr) for smooth surfaces and reduced damage |
5.2 Complementary Equipment
| Equipment | III-V Role | Key Specification |
|---|---|---|
| RIE | Hard mask patterning (SiO₂, SiN), descum, polymer removal | CHF₃/Ar or CF₄/O₂ capability; does not contact III-V directly in most flows |
| IBE/RIBE | Physical etching of metals (Au, Pt contacts), materials without volatile etch products | Multi-angle tilt for re-deposition control; Ar beam + optional reactive gas |
| PECVD | Hard mask deposition (SiO₂, SiN), passivation, encapsulation | Low temperature (< 300 °C) for post-growth processing; low-stress SiN for waveguide cladding |
| ALD | Gate dielectric (Al₂O₃, HfO₂) for MOS-HEMT; conformal passivation of etched sidewalls | Precise thickness control (Å-level); low damage to III-V surface; thermal or plasma-enhanced |
| Sputtering | Hard mask metals (Ni, Cr, Ti), contact metallization, seed layers | Low-damage deposition on III-V surfaces; multi-target for ohmic contact stacks (Ti/Al/Ni/Au for GaN) |
| Coater/Developer | Resist processing for all III-V lithography levels | Standard thin resist (1–2 µm) for photonic features; thick resist for deep mesa |
| Striper | Post-etch resist removal without damaging III-V surfaces | Downstream O₂ plasma (no ion bombardment) to avoid additional III-V surface damage |
| Plasma Cleaner | Pre-deposition surface clean, descum, chamber conditioning | O₂ and Ar plasma; gentle treatment compatible with III-V surface chemistry |
6) Common Failure Modes & Troubleshooting
| Problem | Root Cause | Diagnosis | Solution |
|---|---|---|---|
| Rough etched surface | Non-stoichiometric etching; group-III-rich droplets; micromasking by sputtered material | AFM: > 10 nm RMS; SEM: granular texture or pillars | Increase chemical component (↑ Cl₂/BCl₃ ratio, ↑ pressure); reduce DC bias; add BCl₃ to remove native oxide micromasks |
| Sloped sidewalls | Excessive chemical etching (isotropic component); mask erosion | SEM cross-section: sidewall angle < 85° | Reduce pressure; increase bias power; use harder mask (SiO₂, Ni, Cr instead of photoresist) |
| InCl₃ residue on InP | Substrate temperature too low for InCl₃ volatilization | SEM: white crystalline deposits; XPS: In-rich surface | Increase substrate temperature > 150 °C; switch to CH₄/H₂ chemistry; post-etch HCl dip |
| Polymer buildup (CH₄/H₂) | Carbon-hydrogen polymer deposition exceeds removal rate | SEM: rough mask edges; profilometer: trenching at mask edge; reduced etch rate over time | Add 1–3 sccm O₂ to etch gas; use cyclic etch/O₂-clean; increase Ar component |
| High leakage after gate recess | Ion damage to 2DEG interface; deep-level traps in AlGaN | I-V: increased gate leakage > 10× baseline; C-V: interface state density > 10¹² cm⁻² | Reduce bias power; switch to digital etching; post-etch anneal (400 °C, 1 min, N₂) |
| Etch rate drift | Chamber condition change (polymer buildup, wall coating, MFC drift) | Run-to-run rate variation > ±5% | Regular chamber clean (O₂ + Ar plasma); season with dummy wafers; verify MFC calibration |
| Poor selectivity at heterointerface | Chemistry not optimized for compositional contrast; over-etching | TEM: etch extends into stop layer; device: threshold shift | Tune BCl₃/SF₆ ratio for GaN/AlGaN; use in-situ OES or reflectometry endpoint; switch to digital etch for final nm |
| Mask undercut | Isotropic component at mask edge; resist adhesion failure on III-V surface | SEM: lateral etch > 10% of depth; resist lifting at edges | HMDS or silane adhesion promoter; descum before etch; use hard mask; reduce pressure |
7) Emerging Trends
7.1 Atomic Layer Etching (ALE) for III-V
ALE provides monolayer-level depth control by separating the surface modification (e.g., Cl₂ adsorption) and removal (Ar⁺ bombardment) steps. For III-V gate recess and quantum well trimming, ALE achieves < 0.5 nm/cycle removal with minimal subsurface damage. Key demonstrations include GaN ALE using Cl₂/Ar cycling (0.3 nm/cycle) and InP ALE with O₂/CH₄ cycling. For process fundamentals, see our Atomic Layer Etching Guide.
7.2 Heterogeneous Integration (III-V on Si)
Bonding III-V epitaxial layers to silicon substrates (for photonic integration with CMOS) creates new etching challenges: III-V/bonding-layer/Si material stacks, thermal expansion mismatch stresses, and the need to etch III-V selectively over Si and vice versa. Direct epitaxial growth of GaN on Si (power devices) and InP on Si (photonics) also requires etch processes tolerant of higher defect densities.
7.3 Ultra-Wide-Bandgap Materials (β-Ga₂O₃, AlN, Diamond)
Next-generation power and RF devices are exploring materials beyond GaN: β-Ga₂O₃ (bandgap 4.8 eV), AlN (6.2 eV), and diamond (5.5 eV). These materials are even more chemically inert than GaN, requiring high-density ICP-RIE with BCl₃/Cl₂/Ar at elevated bias powers or novel etch chemistries still under development.
7.4 Damage-Free Etching for Quantum Devices
III-V quantum dots (InAs/GaAs) and nanowire quantum devices require near-zero etch damage to preserve quantum coherence. Techniques include neutral beam etching (ion deflection removes charged species), photo-assisted etching (UV light activates surface reactions), and all-digital approaches combining ALD passivation with selective atomic-layer removal.
8) Practical Recommendations
For Labs Starting III-V Etching
- Start with Cl₂/BCl₃ on GaAs. GaAs is the most forgiving III-V material — etch products are volatile at room temperature, the process window is wide, and results are immediately visible. Master this before moving to GaN or InP.
- Invest in a heated substrate stage if processing InP. Without substrate heating (> 150 °C), Cl₂-based etching of InP leaves non-volatile InCl₃ residues. Alternatively, use CH₄/H₂ chemistry (room temperature) but budget for more frequent chamber cleans.
- Use hard masks for deep etches. Photoresist selectivity over III-V compounds is typically 3–5:1 in Cl₂-based ICP-RIE — insufficient for > 2 µm deep etches. PECVD SiO₂ (selectivity 10–30:1), sputtered Ni (> 50:1), or evaporated Cr (> 30:1) are standard hard mask materials.
- Characterize damage on test structures first. Before etching real devices, run TLM patterns and Schottky diodes through your etch process. Compare contact resistance and ideality factor to unetched controls — this quantifies the damage your process introduces.
- Plan for post-etch surface treatment. Almost every III-V etch process benefits from post-etch surface treatment: HCl dip (oxide removal), (NH₄)₂S passivation (dangling bond saturation), or citric acid clean (damage layer removal). Build these into your process flow from the start.
Equipment Priority Checklist
| Priority | Equipment | III-V Criticality | Rationale |
|---|---|---|---|
| 1 | ICP-RIE | Essential | Primary etch platform for all III-V materials; independent plasma/bias control critical for damage management |
| 2 | PECVD | Essential | Hard mask deposition (SiO₂, SiN); passivation; waveguide cladding |
| 3 | Coater/Developer | Essential | Photoresist processing for all lithography levels |
| 4 | Sputtering | High | Hard mask metals (Ni, Cr); contact metallization (Ti/Al/Ni/Au for GaN) |
| 5 | RIE | High | Hard mask patterning (SiO₂/SiN etch); descum; O₂ clean between CH₄/H₂ etch cycles |
| 6 | ALD | Moderate–High | Gate dielectric for MOS-HEMT; sidewall passivation; ALE-compatible processing |
| 7 | Striper | Moderate | Low-damage resist removal; downstream plasma avoids additional III-V surface damage |
| 8 | IBE/RIBE | Moderate | Metal contact patterning; materials without volatile etch products |
| 9 | Plasma Cleaner | Moderate | Pre-deposition surface prep; chamber conditioning |
Further Reading
- Reactive Ion Etching (RIE) – Principles, Applications, and Equipment Guide
- ICP-RIE Technology – High-Density Plasma for Advanced Etching
- Etching Beyond Silicon: Plasma Processing Challenges for Emerging Materials
- The Selectivity Challenge: Ultra-High Etch Selectivity in Modern Plasma Processes
- Atomic Layer Etching (ALE) – Practical Guide
- Atomic Layer Deposition (ALD) – Comprehensive Guide
- PECVD Complete Guide
- Post-Etch Cleaning & Residue Removal
- Process Chamber Materials & Contamination Control