Atomic Layer Etching (ALE): A Practical Guide for Research and Development

By NineScrolls Engineering · 2025-10-15 · 22 min read · Nanotechnology

As semiconductor devices shrink toward sub-nanometer critical dimensions, conventional plasma etching is reaching its precision limits. Atomic Layer Etching (ALE) has emerged as a transformative approach that offers monolayer-level control over material removal — enabling researchers and process engineers to etch with a precision that was unimaginable just a decade ago.

This guide provides a comprehensive overview of ALE: how it works, how it compares to traditional reactive ion etching (RIE), its key applications in research, and how you can begin exploring ALE processes using ICP-RIE equipment in your own lab.

What Is Atomic Layer Etching?

Atomic Layer Etching is a cyclic, self-limiting etch process that removes material one atomic layer at a time. Unlike continuous plasma etching — where ions and reactive species simultaneously bombard the substrate — ALE separates the process into two distinct, sequential steps:

Step 1 — Surface Modification: A reactive gas (e.g., Cl₂, BCl₃, or fluorocarbon-based chemistry) is introduced to chemically modify only the topmost atomic layer of the target material. This step is self-limiting: once the surface is fully reacted, excess gas molecules do not penetrate deeper.

Step 2 — Removal: A low-energy ion beam or inert gas plasma (typically Ar) is used to selectively remove the modified surface layer through physical sputtering. Because the unmodified material underneath has a higher sputtering threshold, only the reacted layer is removed.

This two-step cycle is repeated until the desired etch depth is achieved, with each cycle removing approximately 0.5–2 Å of material depending on the substrate and chemistry.

ALE vs. Continuous Plasma Etching

The key advantage of ALE is not speed — it is precision. For applications where sub-nanometer depth control, minimal surface damage, and near-perfect uniformity matter more than throughput, ALE offers a fundamentally superior approach.

Core ALE Chemistries and Material Systems

Silicon and Silicon Dioxide

The most established ALE processes target Si and SiO₂. For silicon, a common approach uses:

• Modification step: Cl₂ plasma exposure at low bias to chlorinate the top Si layer
• Removal step: Ar⁺ ion bombardment at 15–30 eV to sputter the SiClₓ layer

For SiO₂, fluorocarbon-based modification (e.g., C₄F₈ or CHF₃) followed by Ar⁺ bombardment has been demonstrated with etch-per-cycle (EPC) values around 1–2 Å.

Research Highlight — Si ALE with Angstrom-Level Control: In a landmark study by Kanarik et al. at Lam Research, Cl₂/Ar ALE of silicon demonstrated an EPC of 1.2 Å/cycle with < 3% non-uniformity across a 300 mm wafer. The self-limiting behavior was confirmed by showing that EPC saturated after 5 seconds of Cl₂ exposure and 10 seconds of Ar bombardment at 25 eV.

III-V Semiconductors (GaN, GaAs, InP)

ALE of III-V materials is gaining interest for power electronics and photonics applications. Cl₂/Ar-based ALE of GaN has been demonstrated with significantly reduced surface damage compared to continuous ICP etching — a critical advantage for HEMT device performance.

Research Highlight — GaN Gate Recess by ALE: Researchers at the University of California, Santa Barbara demonstrated Cl₂/Ar ALE for GaN HEMT gate recess etching with an EPC of ~1.5 Å/cycle. The key finding was that the ALE-etched surface showed a 10x reduction in surface trap density compared to conventional ICP-etched surfaces, as measured by X-ray photoelectron spectroscopy (XPS).

Metals and High-k Dielectrics

ALE of metals such as W, Co, and Ru is being explored for advanced interconnect patterning. Oxidation-based approaches (O₂ modification + low-energy Ar removal) and halogenation-based approaches both show promise for these emerging applications.

Research Highlight — HfO₂ ALE via Ligand Exchange: A novel approach for ALE of high-k dielectrics uses a ligand-exchange mechanism rather than traditional ion-assisted removal. In this process, the HfO₂ surface is first fluorinated using HF vapor, then the fluorinated layer is removed by exposure to a metal-organic precursor (e.g., trimethylaluminum) that undergoes a thermally driven ligand exchange, volatilizing the surface as organometallic products. This “thermal ALE” approach achieves self-limiting removal at 250–300°C without any ion bombardment at all — enabling damage-free etching of ultrathin gate dielectrics.

Emerging Material Systems: Ferroelectrics and Phase-Change Materials

ALE is being extended to materials critical for next-generation memory. Hafnium zirconium oxide (HZO), a ferroelectric material central to FeRAM and FeFET devices, presents unique ALE challenges because its ferroelectric properties are extremely sensitive to surface damage and stoichiometry changes.

Phase-change materials (GST — Ge₂Sb₂Te₅) for PCM and selector devices also benefit from ALE approaches. Conventional etching of GST causes composition segregation that degrades switching characteristics. Cl₂/Ar ALE at 60°C has been shown to maintain the stoichiometric ratio of Ge:Sb:Te to within ±3% of the target 2:2:5 composition across the etched surface, compared to ±15% variation with continuous ICP-RIE.

The ALE Energy Window: Understanding the Self-Limiting Mechanism

The success of ALE hinges on operating within a specific ion energy window during the removal step. Understanding this window is essential for process development:

• Below the modified-layer removal threshold (~10–15 eV for most materials): Ion energy is too low to remove even the modified surface layer. No etching occurs.
• Within the ALE window (~15–50 eV, material-dependent): Ion energy is sufficient to remove the modified layer but too low to sputter the unmodified bulk material. This is the self-limiting regime.
• Above the bulk sputtering threshold (~50–80 eV): Ion energy is high enough to sputter unmodified material, destroying self-limiting behavior. The process reverts to continuous etching.

The width of this energy window determines how robust the ALE process is. Wider windows are more forgiving of plasma non-uniformities and easier to control. Silicon has a relatively wide ALE window (~15–60 eV for Cl₂/Ar), while some III-V materials have narrower windows that demand more precise bias control.

Figure 1: ALE Two-Step Cycle — surface modification and low-energy removal steps with the self-limiting energy window

How to Implement ALE on ICP-RIE Systems

One of the most practical aspects of ALE is that it does not necessarily require a dedicated, purpose-built tool. Many modern ICP-RIE systems can be configured for ALE processes with the right capabilities:

Key Equipment Requirements

1. Pulsed plasma capability: The ability to rapidly switch between modification and removal steps requires fast gas switching and pulsed RF power. Systems with pulsed ICP sources and independently controlled substrate bias are ideal.
2. Low-energy ion control: The removal step requires precise control of ion energy, typically in the 15–50 eV range. This demands independent bias power control at very low power levels — a feature available on advanced ICP-RIE platforms.
3. Fast gas switching: Efficient ALE requires rapid gas exchange between the two steps (ideally < 1 second). Systems with gas injection close to the substrate and effective chamber pumping minimize cycle time.
4. Process recipe flexibility: ALE recipes involve complex timing sequences. Modern process controllers that support step-loop programming and precise timing control simplify recipe development.

NineScrolls\' ICP etching systems feature independent ICP source and substrate bias power controls, pulsed plasma capability, and fast gas delivery — making them well-suited for researchers looking to develop and optimize ALE processes alongside conventional RIE/ICP workflows.

Practical Optimization Challenges and Solutions

Optimizing Gas Switching for Minimal Cycle Time

Gas switching represents the largest throughput bottleneck in ALE processes. Several strategies can minimize this penalty:

• Fast-switching valves: Employ isolation valves with response times below 100 milliseconds to enable sharp gas transitions without prolonged cross-contamination periods.
• Bypass and divert lines: Design the gas manifold with dedicated bypass pathways that allow the removal-step gas (e.g., Ar) to flow continuously while the modification gas is either diverted or shut off.
• Continuous flow with pulsed plasma: Rather than pulsing the gas itself, maintain continuous flow of both gases and pulse the RF power selectively. This approach avoids gas switching overhead entirely.

Calibrating the Ion Energy Window

A critical and often-overlooked source of error in ALE process development is the assumption that the displayed self-bias voltage directly equals the ion energy at the substrate. In reality:

Actual ion energy at substrate ≈ |V_bias| + V_plasma

where V_plasma (the bulk plasma potential) typically ranges from 10–20 eV depending on the gas, pressure, and ICP source power. This means that a displayed bias voltage of 20 V may result in ion energies of 30–40 eV at the substrate — potentially pushing the process beyond the intended ALE window.

To precisely characterize the ion energy distribution, a retarding field energy analyzer (RFEA) is the gold standard. For those without access to an RFEA, a practical empirical workaround: Plot EPC vs. displayed bias power over a wide range and identify the saturation region. The plateau in this curve corresponds to the ALE window.

Chamber Conditioning for ALE

ALE processes are more sensitive to chamber wall state than continuous etching processes. Recommended practices:

• Run 5–10 conditioning cycles on a dummy wafer before collecting data on test or device wafers
• Use the same modification and removal parameters as your intended recipe
• Track conditioning drift by plotting EPC vs. wafer number
• Conduct O₂ plasma chamber cleans between distinct ALE campaigns or after switching chemistries

Dealing with Non-Ideal Self-Limiting Behavior

Not all processes achieve perfect self-limiting behavior. Many exhibit “quasi-ALE” behavior where the EPC continues to increase slowly:

• Synergistic etching: Some radical-surface reactions continue slowly and independently of ion bombardment.
• Imperfect radical quenching: Slow radical desorption can blur the boundary between steps.

Practical guideline: Accept EPC variation of less than 5% as “sufficiently self-limiting” for most research applications.

Applications in Current Research

• Gate etch for FinFET and GAA transistors: As gate dimensions approach 5 nm and below, ALE provides the damage-free, atomic-precision etching required for gate recess and channel release processes.
• Photonic device fabrication: Waveguide and resonator structures require ultra-smooth sidewalls to minimize optical scattering loss. ALE can achieve sub-nanometer surface roughness that continuous etching cannot match.
• 2D material processing: Thinning of van der Waals materials (MoS₂, WSe₂, graphene) to precise layer counts requires gentle, self-limiting removal — a natural fit for ALE.
• MEMS/NEMS: Micro- and nano-electromechanical systems with release structures demand high selectivity and damage-free etching to preserve mechanical properties.

Emerging Frontiers: Hybrid and Cryogenic ALE

Hybrid ALE: Combining Thermal and Plasma Steps

Hybrid ALE combines thermally driven modification with plasma-assisted removal (or vice versa). This approach expands the range of available chemistries and can access material systems where purely thermal or purely plasma-based ALE is ineffective. For example, hybrid ALE of Al₂O₃ using fluorination by HF vapor followed by low-energy Ar⁺ removal has achieved EPCs of ~0.5 Å/cycle with exceptional uniformity.

Cryogenic ALE

Performing ALE at cryogenic temperatures (−80°C to −120°C) is an exciting frontier that combines the precision of ALE with the enhanced sidewall passivation of cryo-etching. At low temperatures, the surface modification step can be made even more self-limiting because physisorbed reactive species desorb more slowly, enabling more complete and uniform surface reactions.

Area-Selective ALE

By choosing modification chemistries that react selectively with one material but not another, ALE can achieve effective “infinite” selectivity — etching one material while leaving the adjacent material completely untouched. This area-selective approach is being explored for self-aligned patterning in advanced logic devices.

Multi-Step ALE for Complex Material Stacks

A frontier area is the development of multi-step ALE sequences that can selectively process complex material stacks in a single chamber without breaking vacuum. For example, a three-step ALE process uses: (1) Cl₂/Ar ALE to selectively etch GaN, (2) BCl₃/Ar ALE to selectively etch AlGaN, and (3) O₂/Ar ALE to remove Al₂O₃ passivation — all within the same ICP-RIE chamber with only gas switching between steps. The ability to perform such multi-step ALE sequences depends critically on having a versatile ICP-RIE platform with fast gas switching, independent bias control, and flexible recipe programming — capabilities available on modern research-grade systems like those offered by NineScrolls.

Directional ALE for 3D Architectures

As device architectures become truly three-dimensional (GAA transistors, 3D NAND, vertical nanowires), directional ALE — where the removal step is anisotropic while the modification step is isotropic — becomes essential. By controlling the ion angular distribution during the removal step through substrate bias and pressure optimization, researchers can achieve anisotropic ALE that preferentially etches horizontal surfaces while preserving vertical sidewalls.

Challenges and Practical Considerations

• Throughput: Cyclic processing is inherently slower than continuous etching. Current research focuses on reducing cycle times — some groups have demonstrated sub-second cycle times using continuous plasma with pulsed gas injection.
• Process complexity: Developing ALE recipes requires understanding the interplay between surface chemistry, ion energy thresholds, and gas-phase dynamics. Computational modeling and machine learning are increasingly being used to accelerate ALE process development.
• Material expansion: While ALE of Si, SiO₂, and Si₃N₄ is relatively mature, many other materials lack established ALE recipes. This represents a significant opportunity for research labs.
• Uniformity at wafer scale: While ALE is inherently more uniform than continuous etching due to its self-limiting nature, achieving true atomic-level uniformity across large substrates requires excellent gas distribution and temperature control.

Getting Started with ALE in Your Lab

1. Start with Si or SiO₂ ALE — These are the best-characterized systems with abundant literature on process windows and expected EPC values.
2. Characterize your ion energy range — Use your ICP-RIE system\'s bias control to map the sputtering threshold of your target material.
3. Optimize gas switching — Minimize the transition time between modification and removal steps.
4. Monitor EPC saturation — The hallmark of true ALE is a saturating EPC curve. Verify this for your process by running systematic time-series experiments.
5. Leverage in-situ diagnostics — Optical emission spectroscopy (OES) and ellipsometry can provide real-time feedback on ALE step completion.
6. Benchmark against continuous etching — Compare surface roughness (AFM), damage depth (XPS or SIMS), and uniformity (ellipsometry mapping) to quantify the benefit of ALE.

Industry Adoption: From Research to Production

ALE\'s transition from a laboratory technique to a production-capable process is accelerating. Major equipment vendors including Lam Research, Tokyo Electron (TEL), and Applied Materials have all announced ALE-capable platforms.

For research labs, this industry adoption validates ALE as a technique worth investing in. Process knowledge developed on research-grade ICP-RIE systems — like those from NineScrolls — translates directly to production, as the fundamental ALE mechanisms remain the same regardless of scale.

Conclusion

Atomic Layer Etching represents the next frontier in precision plasma processing. As device architectures demand atomic-scale control, ALE transitions from a research curiosity to an essential capability in the process engineer\'s toolkit. The good news for research labs is that modern ICP-RIE platforms already provide many of the hardware capabilities needed to develop ALE processes — making it accessible without a dedicated ALE tool.

With emerging variants like hybrid ALE, cryogenic ALE, and area-selective ALE pushing the technique into new territory, the coming years will see an expansion of both the materials and applications that ALE can address. Researchers who build ALE expertise now will be well-positioned to lead this transition.

NineScrolls offers ICP and RIE etching systems designed with the flexibility and precision control that ALE process development requires. To learn more about how our systems can support your ALE research, visit our Products page or request a quote.

Frequently Asked Questions

References and Further Reading

1. Oehrlein, G. S., et al. “Future of plasma etching for microelectronics: Challenges and opportunities.” J. Vac. Sci. Technol. B 42, 041501 (2024). doi:10.1116/6.0003579
2. Kanarik, K. J., et al. “Overview of atomic layer etching in the semiconductor industry.” J. Vac. Sci. Technol. A 33, 020802 (2015). doi:10.1116/1.4913379
3. Faraz, T., et al. “Atomic layer etching: What can we learn from atomic layer deposition?” ECS J. Solid State Sci. Technol. 4, N5023 (2015).
4. George, S. M., & Lee, Y. “Prospects for thermal atomic layer etching using sequential, self-limiting fluorination and ligand-exchange reactions.” ACS Nano 10, 4889 (2016).
5. Tan, S., et al. “Atomic layer etching: A new paradigm for achieving atomic-scale precision in nanofabrication.” Appl. Phys. Rev. 8, 011306 (2021).