Samsung Publishes First System-Level Proof That Hybrid Copper Bonding Cuts HBM Stack Height 15% and Beats TCB on Heat

By NineScrolls Team · 2026-07-04 · 4 min read · Industry

What Samsung Actually Measured

Samsung Electronics has published what it describes as the first quantitative, system-level evidence that hybrid copper bonding (HCB) manages heat better than the thermo-compression bonding (TCB) used in today's high-bandwidth memory. The IEEE paper, "System-Level Thermal Characterization of Hybrid Cu Bonding HBM with 2.5D Advanced Packaging," appeared in June 2026.

Rather than stopping at chip- or package-level simulation, Samsung's team built a physics-based multi-scale model spanning chip-level microstructures up through the package and server-system levels — then validated it with hardware. HCB- and TCB-based HBM test vehicles were mounted alongside an ASIC test chip on a silicon interposer and measured under air cooling that approximates real server operation.

Why the Bond Line Governs Heat in 16-Hi Stacks

HBM stacks DRAM dies vertically — 8, 12, and now 16 layers — beside the AI processor, interconnected by thousands of through-silicon vias. Every added layer traps more heat mid-stack, and much of it must escape downward through the compute die. As stacks climb, heat — not electrical performance — becomes the limiting factor. (For the process foundations, see our guide to through-silicon vias.)

TCB joins dies with micro solder bumps and fills the gaps with non-conductive underfill, which sits directly in the heat path and acts like insulation. HCB eliminates bumps and underfill entirely, fusing copper pads of adjacent dies copper-to-copper — the trade-offs we break down in our comparison of hybrid bonding vs. micro-bump interconnects. Direct metal contact opens many more thermal conduction paths, and removing the bumps makes the whole stack more than 15% shorter.

The Results: Cooler Hotspots, Thinner Stacks, More Power Headroom

Under matched air-cooling conditions, the HCB test vehicles showed lower hotspot junction temperatures than TCB, reduced thermal interference between the memory stack and the logic die beneath it, and a higher usable power budget — headroom that translates directly into sustained performance. Package stack height dropped by more than 15%.

The measured data backs the claim Samsung made at NVIDIA GTC 2026, where it said its HCB approach reduces thermal resistance by more than 20% compared with TCB while enabling stacks of 16 layers or more. Thermal behavior at this stack height is exactly the challenge we examined in our analysis of the thermal and materials challenges of 16-hi HBM.

Roadmap: HCB at 16-Hi HBM4E, Full Hybrid Bonding at HBM5

Samsung plans to introduce HCB with 16-layer HBM4E, running it alongside conventional TCB at first, then moving to full hybrid bonding at HBM5. That differentiates its path from SK hynix, which has leaned on MR-MUF (mass reflow-molded underfill) and treated hybrid bonding as a later-stage option.

The company says the predictive thermal design framework from the study will be used for bonding evaluation and thermal optimization in next-generation HPC packaging. Separately, Samsung reported encouraging HBM4E reliability and yield test progress on July 1 — a signal that qualification work for the 16-hi generation is advancing.

The Catch: Cost, Cleanliness, and Yield

Samsung acknowledges why the industry has researched hybrid bonding for years without putting it into volume HBM production: it demands near-perfect surface cleanliness and sub-micron alignment across every die, more expensive equipment, more cleanroom space, and yield risk that compounds as the stack grows taller. Those long-term reliability stakes — warpage, thermal cycling, interconnect fatigue — are the territory of our overview of 3D packaging reliability.

NineScrolls Niche Angle

For plasma processing and thin-film deposition, this paper matters because hybrid bonding is a surface-preparation-intensive process. A production Cu-Cu bond line depends on plasma activation of the dielectric surfaces before bonding, high-quality PECVD or ALD dielectric films, precision CMP, and aggressive wet/dry cleaning — every one of those steps is an equipment purchase. If Samsung phases HCB into 16-hi HBM4E and commits fully at HBM5, demand shifts up the line to plasma activation tools, deposition systems, and the metrology to verify atomically flat surfaces.

The stack itself still rides on TSVs: deep silicon etch, liner deposition, and copper fill remain the backbone of any HBM architecture, hybrid-bonded or not. Readers evaluating process routes should start with our TSV guide and our comparison of hybrid bonding vs. micro-bump; for what taller stacks mean for materials and heat, see our 16-hi HBM thermal deep dive.