Wide Bandgap Semiconductor Device Fabrication – GaN & SiC Dry Etching, Deposition, and Process Integration Guide

By NineScrolls Engineering · 2026-04-19 · 26 min read · Materials Science

Target Readers: Power device process engineers, wide bandgap semiconductor researchers, equipment engineers selecting etch and deposition platforms for GaN/SiC fabrication, R&D procurement teams evaluating ICP-RIE and deposition systems for power electronics labs, and engineers transitioning from silicon power device fabrication to wide bandgap materials.

TL;DR Summary

Wide bandgap (WBG) semiconductors — primarily GaN (3.4 eV) and SiC (3.26 eV for 4H-SiC) — are transforming power electronics, enabling devices that operate at higher voltages, temperatures, and switching frequencies than silicon can achieve. However, the same material properties that make GaN and SiC superior for power devices — strong chemical bonds, high hardness, chemical inertness — make them exceptionally challenging to etch and process. SiC's Si–C bond strength (4.53 eV) makes it nearly impervious to wet chemistry; GaN's wurtzite crystal structure and nitrogen vacancy sensitivity demand careful damage control. This guide covers the complete WBG device fabrication chain: substrate preparation, mesa isolation etching, gate recess processes, ohmic contact formation, passivation and gate dielectric deposition, via etching, and packaging considerations — with practical process windows, failure modes, and equipment selection criteria for each step.

1) Why Wide Bandgap Semiconductors Require Specialized Processing

Silicon power devices (IGBTs, MOSFETs) have served the power electronics industry for decades, but they are approaching fundamental material limits. Silicon's 1.12 eV bandgap constrains breakdown fields to ~0.3 MV/cm, junction temperatures to ~150°C, and electron saturation velocity to ~1×10⁷ cm/s. Wide bandgap materials shatter these limits:

These superior properties come at a fabrication cost: both SiC and GaN are far more difficult to process than silicon. The fabrication challenges fall into three categories:

1.1 Chemical Inertness

SiC: The Si–C bond dissociation energy (4.53 eV) is nearly 50% higher than Si–Si (3.34 eV). SiC is virtually inert to all conventional wet etchants at room temperature — even hot KOH (80°C) etches 4H-SiC at less than 1 nm/min on the Si-face. Dry etching with ICP-RIE is the only practical approach, requiring high ion energies and fluorine-based chemistries (SF₆, CF₄, NF₃) with significant physical sputtering components.

GaN: While less chemically inert than SiC, GaN resists most wet etchants except hot phosphoric acid (H₃PO₄ at 160°C+) and molten KOH, neither of which provides the anisotropy or precision needed for device fabrication. Chlorine-based ICP-RIE (Cl₂/BCl₃) is the standard approach.

1.2 Etch Damage Sensitivity

Power devices operate under high electric fields where crystal damage directly degrades performance. In GaN HEMTs, ion bombardment during gate recess etching creates nitrogen vacancies (V_N) that act as n-type donors, shifting threshold voltage and increasing gate leakage by orders of magnitude. In SiC MOSFETs, subsurface damage at the SiC/SiO₂ interface creates interface traps (D_it > 10¹² cm⁻² eV⁻¹) that degrade channel mobility from theoretical ~900 cm²/V·s to often less than 30 cm²/V·s.

1.3 Process Temperature Extremes

SiC device fabrication routinely involves temperatures that would destroy silicon devices: ion implantation activation at 1600–1700°C, thermal oxidation at 1200–1300°C, and ohmic contact annealing at 900–1050°C. These high-temperature steps constrain the process integration sequence and limit material choices for masking and passivation layers.

Figure 1: Wide Bandgap Material Property Comparison — SiC and GaN offer 3× the bandgap and 10× the critical electric field of silicon, enabling fundamentally different power device architectures

2) SiC Dry Etching: Conquering the Hardest Semiconductor

SiC etching is arguably the most demanding dry etch process in semiconductor manufacturing. The combination of extreme bond strength, high hardness (9.2–9.5 on the Mohs scale, compared to 7 for silicon), and the need for smooth, damage-free surfaces makes SiC etching a process engineering challenge at every step.

2.1 Gas Chemistry for SiC

SiC etching requires fluorine-based chemistries because the etch products — SiF₄ and CF₄ (or CO, CO₂) — are volatile at typical process temperatures. Chlorine-based chemistries, which work well for GaN and other III-V materials, are ineffective for SiC because SiCl₄ formation is thermodynamically unfavorable at the high ion energies needed to break Si–C bonds, and carbon chlorides (CCl₄) have insufficient volatility.

SF₆/O₂ — the workhorse chemistry: SF₆ provides atomic fluorine (F*) for chemical etching of both Si and C. The role of O₂ is critical and multifaceted: (1) O₂ reacts with carbon to form volatile CO and CO₂, preventing carbon-rich residue buildup that would otherwise slow or stop the etch; (2) O₂ also reacts with sulfur from SF₆ decomposition, preventing sulfur redeposition; (3) the SF₆:O₂ ratio controls the balance between F* radical generation and carbon removal. Typical ratios of 2:1 to 4:1 (SF₆:O₂) optimize etch rate while maintaining smooth surfaces.

O₂ flow tuning: Too little O₂ leads to carbon-rich surface residues (appearing as black or brown discoloration) that slow etching and create roughness. Too much O₂ dilutes F* concentration, reducing etch rate, and can oxidize the SiC surface during etching, creating an SiO₂-like surface layer that acts as a micro-mask and increases roughness. The optimal O₂ window is typically 15–30% of total gas flow.

2.2 ICP-RIE Process Parameters for SiC

SiC etching demands higher ion energies than silicon or III-V etching because the Si–C bonds must be broken by physical bombardment before chemical etching can proceed efficiently. This makes the DC bias (controlled by RIE/platen power) the most critical parameter.

Critical insight — the damage-rate tradeoff: SiC etching operates in a fundamentally different regime from silicon etching. In silicon ICP-RIE, chemical etching dominates and ion bombardment primarily provides directionality. In SiC ICP-RIE, physical sputtering is essential to initiate the etch — ions must deliver enough energy to break Si–C bonds before fluorine radicals can attack the disrupted surface. This means SiC etch processes inherently cause more subsurface damage than equivalent silicon processes. The process engineer's challenge is finding the minimum ion energy that sustains acceptable etch rates while keeping damage within device tolerance.

2.3 SiC Etch Challenges and Solutions

Micromasking and surface roughness: The most common SiC etch defect is "micromasking" — micro-scale residue particles on the surface that locally block etching, creating needle-like protrusions (grass) or increased roughness. Sources include: (1) sputtered mask material (especially metal hard masks like Ni or Cr), (2) non-volatile etch byproducts, (3) chamber contamination. Solutions:

• Use SiO₂ hard masks instead of metal: PECVD SiO₂ (or thermally grown oxide) produces only volatile sputter products (SiF₄, SiO) and eliminates metal contamination. Selectivity of SiC:SiO₂ = 3:1 to 5:1 with SF₆/O₂.
• Optimize O₂ fraction: Sufficient O₂ (15–30%) removes carbon residues that act as micro-masks.
• Increase substrate temperature: Heating the platen to 100–250°C improves etch product volatility, reducing redeposition. Some advanced processes use 300°C+ for ultra-smooth surfaces.
• Post-etch surface treatment: Sacrificial oxidation (dry O₂ at 1150°C for 30 min, then HF strip) removes 20–50 nm of damaged SiC and significantly reduces surface roughness.

Etch depth uniformity for power devices: SiC power devices (MOSFETs, JBS diodes) require mesa depths of 0.5–3 μm with uniformity better than ±5% across 150 mm wafers. Achieving this requires:

• Uniform ICP plasma density (verified by Langmuir probe or etch rate mapping)
• Controlled wafer temperature (electrostatic chuck with He backside cooling)
• Endpoint detection — laser interferometry for precise depth control on gate trench etching

3) GaN Etching for Power Devices

GaN power device etching shares some chemistry with the RF/photonics GaN etching covered in our III-V Compound Semiconductor Etching Guide, but power device fabrication introduces unique challenges: deeper mesa isolation (1–5 μm for high-voltage devices), precision gate recess etching for enhancement-mode (E-mode) operation, and via etching through the GaN buffer to the SiC or Si substrate for thermal and electrical grounding.

3.1 GaN Power Device Etch Steps

A typical GaN-on-SiC power HEMT fabrication flow involves four distinct etch steps, each with different requirements:

3.2 Gate Recess: The Most Critical Etch in GaN Power Devices

Enhancement-mode (normally-off) GaN HEMTs require recessing the AlGaN barrier to deplete the 2DEG channel beneath the gate. The target recess depth is typically 15–25 nm in a 20–30 nm AlGaN barrier — meaning the etch must stop within a few nanometers of the AlGaN/GaN interface without penetrating it. This is arguably the most demanding etch step in all of power device fabrication.

The fundamental challenge: Over-etching by just 2–3 nm degrades 2DEG density, increases on-resistance, and shifts threshold voltage. Under-etching leaves the device in depletion mode (normally-on), defeating the purpose of the recess. The etch must be uniform to ±1 nm across the wafer to achieve tight V_th distributions.

Approach 1 — Low-power ICP-RIE: BCl₃/Cl₂ at very low RIE power (5–20 W, DC bias < −30 V) with high ICP power (200–400 W). Etch rate: 2–5 nm/min. Timed etch with in-situ reflectometry or ellipsometry for endpoint detection. Achieves ±2–3 nm uniformity with careful calibration.

Approach 2 — Digital etching (ALE-like): Alternating (1) low-power oxidation step (O₂ plasma, 10–30 s) that converts 1–2 nm of GaN/AlGaN surface to oxide, followed by (2) dilute acid dip (HCl or HF) or BCl₃ plasma to selectively remove the oxide. Each cycle removes ~1 nm. Achieves ±1 nm depth control but requires multiple cycles (15–25 cycles for a full recess), increasing process time.

Approach 3 — Selective etch with etch-stop: BCl₃/SF₆ chemistry exploits AlF₃ formation as a natural etch-stop on aluminum-containing layers. Selectivity of GaN over AlGaN can reach 5–20:1, enabling endpoint-free processing. Requires careful SF₆ flow optimization — too much SF₆ attacks the AlGaN.

Figure 2: SiC vs GaN ICP-RIE Etch Process Comparison — SiC requires fluorine-based chemistry with high ion energy, while GaN uses chlorine-based chemistry with lower damage thresholds

3.3 Damage Mitigation in GaN Power Device Etching

Plasma-induced damage is the single largest yield limiter in GaN power device fabrication. The mechanisms and solutions differ from RF GaN devices because power devices operate under much higher electric fields where even minor crystal damage creates catastrophic leakage:

Post-etch recovery sequence for gate recess: A proven sequence for recovering gate recess damage in GaN HEMTs: (1) TMAH (25%, 60°C, 30 min) — removes 2–3 nm of damaged surface and smooths sidewalls; (2) (NH₄)₂S passivation (21%, RT, 20 min) — replaces surface oxides with sulfur termination; (3) immediate transfer to ALD chamber (< 5 min air exposure) for gate dielectric deposition. This sequence typically recovers 50–80% of the V_th shift caused by plasma damage.

4) Thin Film Deposition for WBG Devices

WBG device fabrication relies heavily on deposited thin films for passivation, gate dielectrics, interlayer dielectrics, and encapsulation. The requirements differ significantly from silicon processing due to higher operating temperatures, different interface chemistry, and the critical importance of interface quality.

4.1 Passivation Films (PECVD SiN_x)

PECVD silicon nitride (SiN_x) is the primary passivation material for both GaN HEMTs and SiC devices. In GaN HEMTs, the SiN_x passivation serves a dual role: (1) surface passivation to eliminate trap states that cause current collapse (a.k.a. dynamic R_on degradation), and (2) field plate dielectric for voltage shaping.

PECVD recipe optimization for GaN: The SiH₄:NH₃ ratio controls film stoichiometry and stress. Si-rich films (SiH₄:NH₃ > 1:1) have lower hydrogen content, fewer N–H bonds, and reduced electron trapping — critical for minimizing current collapse. Deposition at 300–350°C (vs 250°C) further reduces hydrogen incorporation. A typical optimized recipe: SiH₄ 40 sccm, NH₃ 20 sccm, N₂ 400 sccm, 300°C, 900 mTorr, 100 W RF → 50 nm/min, n = 2.05, stress = +100 MPa tensile.

4.2 Gate Dielectrics (ALD Al₂O₃, HfO₂)

MIS-HEMT (metal-insulator-semiconductor HEMT) architectures use a gate dielectric between the gate metal and the AlGaN surface to reduce gate leakage. ALD-deposited Al₂O₃ is the most widely used gate dielectric for GaN power devices because of its high breakdown field (~10 MV/cm), good thermal stability, and favorable band alignment with AlGaN.

ALD Al₂O₃ on GaN: TMA (trimethylaluminum) + H₂O process at 250–300°C. Growth rate: 0.1 nm/cycle. Typical thickness: 10–25 nm. The first few ALD cycles are critical — TMA must react with the GaN surface (not with native oxide), so pre-deposition surface preparation (HCl dip + in-situ N₂H₄ or TMA pre-pulse) directly determines interface quality. D_it values of 10¹¹–10¹² cm⁻² eV⁻¹ are achievable with optimized surface prep; without it, D_it exceeds 10¹³ cm⁻² eV⁻¹.

Gate oxide for SiC MOSFETs: The SiC/SiO₂ interface is the Achilles' heel of SiC MOSFET technology. Thermal oxidation of SiC creates a high density of interface traps (primarily carbon clusters and near-interface traps) that severely degrade channel mobility. Current state-of-the-art approaches:

• NO (nitric oxide) anneal: Post-oxidation anneal in NO at 1175°C for 60–120 min. Nitrogen passivates interface traps, reducing D_it by ~10× and improving channel mobility from 5–10 cm²/V·s to 30–50 cm²/V·s.
• POCl₃ anneal: Phosphorus incorporation at the SiC/SiO₂ interface. Can achieve channel mobility > 80 cm²/V·s but raises reliability concerns.
• Deposited dielectrics: ALD Al₂O₃ or HfO₂ directly on SiC (bypassing thermal oxidation). Still in research stage but showing promise for D_it reduction.

4.3 Metal Contact Deposition

GaN ohmic contacts: Ti/Al/Ni/Au (20/120/40/50 nm) stack is the standard for n-GaN contacts. Requires rapid thermal annealing (RTA) at 830–870°C for 30 s in N₂ to form TiN at the Ti/GaN interface, achieving contact resistance < 0.5 Ω·mm. Sputter deposition provides better step coverage and adhesion than e-beam evaporation for these multi-layer stacks.

SiC ohmic contacts: Ni (100 nm) on n-type SiC, annealed at 950–1050°C to form Ni₂Si. Contact resistance < 10⁻⁵ Ω·cm². Ti/Al on p-type SiC requires higher anneal temperatures (1000–1100°C).

Figure 3: WBG Device Fabrication Process Flows — GaN HEMT (top) and SiC MOSFET (bottom) share similar unit processes but differ significantly in process temperatures and integration sequence

5) Process Integration: Complete Device Flows

5.1 GaN-on-SiC Power HEMT Process Flow

A typical enhancement-mode GaN HEMT fabrication on SiC substrate follows this sequence:

1. Wafer clean: Solvent clean → HCl (1:1, 10 min) → DI rinse → N₂ dry
2. Alignment marks: ICP-RIE etch (Cl₂/BCl₃, 200 nm deep) or metal lift-off
3. Mesa isolation: ICP-RIE etch (Cl₂/BCl₃/Ar, 300–500 nm) with photoresist mask. Smooth sidewalls critical for voltage blocking.
4. Ohmic contact formation: BOE surface clean → Ti/Al/Ni/Au sputter deposition → lift-off → RTA 850°C/30 s in N₂
5. Gate recess etch: Low-power ICP-RIE or digital etch (see Section 3.2). Critical step — determines V_th.
6. Gate dielectric: (NH₄)₂S surface treatment → ALD Al₂O₃ (20 nm at 250°C). Must be deposited within minutes of surface treatment.
7. Gate metal: Ni/Au (50/300 nm) or TiN/Al by sputter deposition + lift-off
8. First passivation: PECVD SiN_x (100–200 nm at 300°C). Controls surface states and current collapse.
9. Field plate formation: Via etch through SiN_x → metal deposition → patterning
10. Thick passivation: PECVD SiN_x or SiO₂ (0.5–2 μm) for voltage isolation
11. Via/pad opening: RIE etch through passivation stack to bond pads
12. Backside processing: Wafer thinning → via etch through SiC substrate (SF₆/Ar ICP-RIE) → backside metallization

5.2 SiC MOSFET Process Flow

SiC MOSFET fabrication is more complex than GaN HEMT processing due to the need for ion implantation (which requires 1600°C+ activation) and thermal gate oxidation:

1. Starting material: n⁻ epitaxial layer on n⁺ 4H-SiC substrate (4° off-axis)
2. P-well implantation: Al⁺ ions at multiple energies (30–400 keV) → activation anneal at 1650°C in Ar with carbon cap
3. N⁺ source implantation: N⁺ ions → activation at 1650°C
4. Carbon cap removal: O₂ plasma or thermal oxidation
5. Sacrificial oxidation: Thermal oxidation at 1150°C → HF strip. Removes implant damage from surface.
6. Gate trench etch: ICP-RIE (CF₄/O₂ or SF₆/O₂, low bias) for trench-gate MOSFETs. Depth: 0.3–1 μm. Smooth trench bottom and corners are critical.
7. Gate oxidation: Thermal oxidation at 1200–1300°C → NO anneal at 1175°C for interface passivation
8. Gate electrode: Doped polysilicon deposition → patterning by RIE
9. ILD deposition: PECVD SiO₂ (0.5–1 μm) + densification anneal
10. Contact via etch: RIE through ILD to source/drain regions
11. Ohmic contacts: Ni sputter deposition → RTA at 1000°C → Ni₂Si formation
12. Metallization: Al or Al/Cu by sputtering → patterning
13. Passivation: PECVD SiN_x + polyimide
14. Backside contact: Wafer thinning → Ni/Ag/Au backside metallization

6) Equipment Selection for WBG Device Fabrication

6.1 ICP-RIE System Requirements

WBG device fabrication places unique demands on ICP-RIE systems compared to silicon processing:

Single-chamber vs. multi-chamber strategy: For R&D labs processing both SiC and GaN, a single ICP-RIE chamber with both F-based and Cl-based gas lines is practical and cost-effective, provided thorough chamber conditioning is performed between material changeovers (O₂ plasma clean → conditioning wafer). For production, dedicated chambers for each chemistry are preferred to eliminate cross-contamination risk.

6.2 Deposition System Requirements

• PECVD: Must support low-stress SiN_x deposition at 250–350°C with controlled SiH₄:NH₃ ratio. Film stress characterization capability (wafer bow measurement) is essential for GaN passivation development. Dual-frequency RF (13.56 MHz + 380 kHz LF) enables independent stress tuning.
• ALD: Required for gate dielectrics (Al₂O₃, HfO₂). Must achieve < 10¹² cm⁻² eV⁻¹ interface trap density. Thermal ALD (not plasma-enhanced) is preferred for GaN gate dielectrics to avoid additional plasma damage. Fast chamber purge for high throughput.
• Sputtering: Multi-target capability for metal contact stacks (Ti/Al/Ni/Au for GaN; Ni for SiC). Good step coverage for via filling. Substrate heating (up to 400°C) for improved film adhesion and density.

Figure 4: WBG Device Fabrication Equipment Ecosystem — From ICP-RIE etching through deposition and characterization, each tool must meet the demanding requirements of wide bandgap materials

7) Common Failure Modes and Troubleshooting

8) Emerging Trends

8.1 Vertical GaN Power Devices

While lateral GaN HEMTs dominate today's market, vertical GaN devices (trench MOSFETs, current-aperture vertical electron transistors — CAVETs) are emerging for voltage ratings above 1200 V. These devices require deep trench etching (3–10 μm) in GaN with smooth, damage-free sidewalls — a process that pushes GaN ICP-RIE to its limits. Trench sidewall smoothing by TMAH-based wet etching after dry etch is showing promise for achieving the required crystal quality.

8.2 GaN-on-GaN: The Next Frontier

Native GaN substrates (instead of GaN-on-SiC or GaN-on-Si) eliminate lattice mismatch and enable vertical device architectures with lower defect densities. However, GaN substrates are extremely expensive ($3,000–5,000 per 2-inch wafer) and limited to small sizes (2–4 inch), making yield-critical processing and precise etch control even more important. Every wafer lost to process defects represents a significant cost penalty.

8.3 Ultra-Wide Bandgap Materials

Looking beyond GaN and SiC, ultra-wide bandgap (UWBG) materials are emerging for extreme-voltage applications:

• β-Ga₂O₃ (4.8 eV): Bandgap exceeds both GaN and SiC. BCl₃/Ar ICP-RIE achieves 50–100 nm/min etch rates. Major challenge: no p-type doping available, limiting device architectures.
• AlN (6.2 eV): Extremely high breakdown field (~15 MV/cm). Requires Cl₂/BCl₃/Ar at high ICP power for etching. Applications in deep UV photonics and extreme-environment electronics.
• Diamond (5.5 eV): Ultimate thermal conductivity (2200 W/m·K). O₂/Ar ICP-RIE etching at 5–50 nm/min. Diamond-based power devices remain in early research.

9) References and Further Reading

• Pearton, S. J., et al. "Plasma etching of wide bandgap semiconductors." Plasma Processes and Polymers, 2(1), 16–37 (2005). doi:10.1002/ppap.200400035
• Khan, F. A., et al. "High rate etching of SiC using inductively coupled plasma reactive ion etching in SF₆-based gas mixtures." Applied Physics Letters, 75(15), 2268 (1999). doi:10.1063/1.124985
• Burnham, S. D., et al. "Gate-recessed normally-off GaN-on-Si HEMT using a new O₂-BCl₃ digital etching technique." Physica Status Solidi (c), 7(7-8), 2010–2012 (2010). doi:10.1002/pssc.200983643
• Kimoto, T. & Cooper, J. A. Fundamentals of Silicon Carbide Technology. Wiley-IEEE Press (2014). ISBN 978-1118313527
• Amano, H., et al. "The 2018 GaN power electronics roadmap." Journal of Physics D: Applied Physics, 51, 163001 (2018). doi:10.1088/1361-6463/aaaf9d
• Roccaforte, F., et al. "Emerging trends in wide band gap semiconductors (SiC and GaN) technology for power devices." Microelectronic Engineering, 187-188, 66–77 (2018). doi:10.1016/j.mee.2017.11.021

Related articles:

• III-V Compound Semiconductor Etching Guide — detailed GaN etch chemistry for RF and photonics applications
• ICP-RIE Technology Guide — fundamentals of high-density plasma etching
• Atomic Layer Etching (ALE) Guide — digital etching techniques applicable to GaN gate recess
• PECVD Complete Guide — passivation film deposition for WBG devices
• ALD Guide — gate dielectric deposition for GaN MIS-HEMTs