Solar Cell Manufacturing: Renewable Energy Solutions

By NineScrolls Engineering · 2024-01-12 · 21 min read · Energy

Target Readers: Photovoltaic process engineers, solar cell researchers, thin-film scientists, and equipment evaluators working on crystalline silicon, perovskite, CIGS, CdTe, or tandem solar cell fabrication. Assumes familiarity with cleanroom operations and basic semiconductor processing. Newcomers will find the process comparison tables and starter recipes useful; experienced engineers can skip to the technology-specific sections and troubleshooting guide.

TL;DR Summary

Solar cell fabrication is fundamentally a thin-film and plasma processing challenge. Every high-efficiency cell architecture — from mainstream PERC/TOPCon crystalline silicon to emerging perovskite and tandem designs — relies on precise control of deposition, etching, and surface modification steps. This guide provides actionable process parameters for each critical step: KOH/IPA wet texturing and ICP-RIE black silicon formation, PECVD SiN_x anti-reflection coating (SiH₄/NH₃, n = 2.0, 75 nm, 300 °C), ALD Al₂O₃ rear passivation (TMA/H₂O, 200 °C, 1.1 Å/cycle), sputtered TCO electrodes and absorber layers, and complete perovskite/Si tandem integration flows. Four detailed comparison tables, equipment mapping to NineScrolls products, a troubleshooting guide, and an FAQ section provide everything needed to select, set up, and optimize solar cell processes.

1) Why Thin-Film and Plasma Processing Define Solar Cell Efficiency

The photovoltaic industry has achieved crystalline silicon (c-Si) module efficiencies exceeding 24% in production and perovskite/Si tandem cells surpassing 33% in the laboratory. These gains are driven almost entirely by improvements in thin-film processing — better anti-reflection coatings, superior surface passivation, cleaner interfaces, and more conformal depositions on textured surfaces. The difference between a 20% cell and a 26% cell is not the silicon wafer itself but the quality of the films deposited on it and the surfaces prepared beneath them.

Three processing domains determine cell performance:

Surface texturing: Reducing front-surface reflectance from ~35% (polished Si) to < 2% through wet-chemical pyramidal texturing or plasma-based nanostructuring, directly increasing photocurrent by 2–4 mA/cm².
Passivation and anti-reflection: PECVD SiN_x and ALD Al₂O₃ films reduce surface recombination velocity from > 10⁵ cm/s (bare Si) to < 5 cm/s (passivated), adding 30–80 mV to open-circuit voltage (V_oc).
Electrode and contact deposition: Sputtered transparent conducting oxides (ITO, AZO) and evaporated/screen-printed metal contacts must balance low sheet resistance (< 10 Ω/sq) with minimal parasitic absorption and contact recombination.

This guide covers the plasma and thin-film processes for four major cell architectures — c-Si (PERC/TOPCon), perovskite, CIGS/CdTe, and tandem — with specific recipes, equipment parameters, and practical guidance for each.

2) Crystalline Silicon Solar Cell Processing

2.1 Surface Texturing

Surface texturing is the first critical process step after wafer cleaning. The goal is to create surface features that trap incident light through multiple internal reflections, reducing weighted average reflectance (WAR) across the AM1.5G solar spectrum.

KOH/IPA Alkaline Wet Texturing (Standard c-Si Process)

The industry-standard texturing process for monocrystalline (100) silicon exploits the anisotropic etch rate of KOH, which etches (100) planes ~30x faster than (111) planes, producing random upright pyramids 1–10 μm in height.

Parameter	Typical Range	Optimized Value	Effect on Texture
KOH concentration	1–5 wt%	2 wt%	Higher concentration increases etch rate but produces larger, less uniform pyramids
IPA concentration	3–7 vol%	5 vol%	Acts as surfactant; promotes uniform nucleation of pyramids across wafer
Temperature	70–85 °C	80 °C	Higher temp increases etch rate (~0.5 μm/min at 80 °C) but can reduce uniformity
Etch time	15–40 min	25 min	Longer etch produces taller pyramids; over-etch rounds pyramid tips
WAR after texturing	10–15%	~11%	Before ARC; reduced to < 2% with SiN_x coating
Pyramid height	1–10 μm	3–5 μm	Uniform 3–5 μm pyramids optimize both optical and passivation performance

Limitation: KOH texturing works only on monocrystalline (100) Si. Multicrystalline Si with random grain orientations requires acidic texturing (HF/HNO₃) or plasma-based approaches, as the anisotropic KOH mechanism does not produce uniform pyramids on non-(100) surfaces.

Plasma-Based Black Silicon by ICP-RIE

Black silicon — a surface covered with nanoscale needle-like or cone-shaped features — achieves WAR < 1% across 300–1100 nm without any additional anti-reflection coating. The nanostructures are formed by maskless reactive ion etching in an ICP-RIE system using SF₆/O₂ chemistry, where micro-masking by SiO_xF_y passivation drives self-organized nanostructure formation.

Parameter	Black Silicon Recipe	Notes
ICP source power	1500–2500 W (13.56 MHz)	Controls plasma density and radical production
Substrate bias power	5–20 W	Low bias critical — high bias destroys nanostructures
SF₆ flow	30–50 sccm	Provides F radicals for Si etching
O₂ flow	15–30 sccm	Forms SiO_xF_y micro-mask; O₂/SF₆ ratio ~0.5 is optimal
Pressure	10–30 mTorr	Lower pressure improves directionality; higher pressure increases isotropy
Temperature	−10 to +20 °C	Cryogenic temps enhance passivation; room temp is adequate for most work
Etch time	5–15 min	Needle height increases with time; 10 min produces ~500 nm features
Resulting WAR	< 1%	Broadband across 300–1100 nm; eliminates need for separate ARC

Advantage over wet texturing: Black silicon works on any crystal orientation (including multicrystalline and even amorphous Si), produces sub-wavelength features that eliminate the need for a separate SiN_x ARC layer, and can be integrated with standard ICP-RIE equipment already used in semiconductor and MEMS lines. The main challenge is increased surface area leading to higher surface recombination, which requires excellent passivation (ALD Al₂O₃ is particularly effective on black silicon due to its conformal coverage of high-aspect-ratio nanostructures).

2.2 Emitter Formation

After texturing, the p-n junction is formed by diffusing phosphorus (for p-type base wafers) or boron (for n-type base) into the wafer surface. The standard industrial process uses POCl₃ diffusion at 830–870 °C for 20–40 min, producing a sheet resistance of 80–120 Ω/sq for a selective emitter or 50–60 Ω/sq for a conventional homogeneous emitter. The diffusion profile — specifically the surface concentration (typically 1–5 × 10²⁰ cm⁻³) and junction depth (0.3–0.5 μm) — directly impacts both contact resistance and emitter recombination current density (J_0e).

For advanced TOPCon (Tunnel Oxide Passivating Contact) cells, the emitter side uses a boron-diffused p⁺ layer on an n-type wafer, while the rear contact uses an ultra-thin tunnel oxide (~1.5 nm SiO₂) capped with heavily doped poly-Si deposited by PECVD or LPCVD. The tunnel oxide can be grown thermally or deposited by ALD; the poly-Si cap is typically 100–200 nm of n⁺ doped amorphous silicon deposited by PECVD (SiH₄, 200–250 °C, 0.5–1.0 nm/s) followed by crystallization anneal at 850–900 °C.

2.3 SiN_x Anti-Reflection Coating by PECVD

The silicon nitride anti-reflection coating (ARC) is the single most impactful thin-film deposition step in c-Si solar cell production. A properly optimized SiN_x:H film simultaneously provides three functions: anti-reflection (reducing WAR from ~11% to < 2%), surface passivation (hydrogen passivation of dangling bonds, reducing surface recombination velocity to < 10 cm/s), and bulk passivation (hydrogen release during contact firing migrates into the bulk, passivating crystal defects).

Parameter	Value	Rationale
Deposition method	Direct PECVD (13.56 MHz)	Industry standard; provides high hydrogen content for passivation
Precursors	SiH₄ + NH₃	SiH₄/NH₃ gas ratio controls refractive index and composition
SiH₄/NH₃ flow ratio	1:3 to 1:5	Ratio of ~1:4 targets stoichiometric Si₃N₄ with n = 2.0; Si-rich (1:3) increases n to ~2.1–2.2 with better passivation but higher absorption
Target refractive index (n)	2.0 (at 632 nm)	Optimal ARC condition: n = √(n_glass × n_Si) ≈ √(1.5 × 3.9) ≈ 2.0
Target thickness	75 nm	Quarter-wave condition: d = λ/(4n) = 600/(4 × 2.0) = 75 nm for peak at 600 nm
Substrate temperature	300 °C	Balances film quality with hydrogen retention; lower temp increases H content but reduces film density
RF power density	30–60 mW/cm²	Higher power increases deposition rate but can reduce hydrogen content
Chamber pressure	300–600 mTorr	Higher pressure promotes gas-phase reactions; 400 mTorr is typical
Deposition rate	5–15 nm/min	~8–10 nm/min is typical at 300 °C; faster rates possible at higher power but risk particulate formation
Hydrogen content [H]	10–15 at%	Critical for passivation; released during 700–800 °C contact firing to passivate bulk and surface defects
Film stress	Slightly compressive (50–200 MPa)	Avoids wafer bowing; tensile stress risks cracking on textured surfaces

Process note: The SiN_x:H film is deposited on a PECVD system operating at 13.56 MHz. For high-throughput production, inline PECVD tools process 1000+ wafers/hour in a continuous belt configuration. For R&D and pilot lines, batch PECVD systems with parallel-plate or tube reactor geometries offer more precise control over film properties at the cost of throughput. The key quality metric is the effective minority carrier lifetime (τ_eff) measured after deposition — a good SiN_x passivation on p-type Cz-Si should yield τ_eff > 100 μs on 1 Ω·cm material, increasing to > 500 μs after a contact-firing thermal cycle (700–800 °C, 1–3 s peak).

2.4 ALD Al₂O₃ Rear Passivation

Aluminum oxide (Al₂O₃) deposited by atomic layer deposition is the standard rear-surface passivation layer for PERC (Passivated Emitter and Rear Cell) and TOPCon architectures. Al₂O₃ provides both chemical passivation (reduction of interface trap density D_it to < 10¹¹ cm⁻²eV⁻¹) and field-effect passivation through a high fixed negative charge density (Q_f ~ −10¹³ cm⁻²) that repels minority electrons from the p-type rear surface.

Parameter	Value	Notes
ALD type	Thermal ALD (preferred) or plasma-enhanced ALD	Thermal ALD avoids plasma damage; PEALD offers faster GPC and lower temp operation
Precursors	TMA (trimethylaluminum) / H₂O	TMA/O₃ also used; TMA/H₂O is standard for solar
Substrate temperature	200 °C	ALD window: 150–300 °C; 200 °C balances GPC stability, film quality, and hydrogen incorporation
Growth per cycle (GPC)	1.0–1.2 Å/cycle	~1.1 Å/cycle typical at 200 °C; decreases above 250 °C due to TMA desorption
Target thickness	10–15 nm	~100–135 ALD cycles; thicker films do not improve passivation; thinner films risk pinholes
TMA pulse time	15–30 ms	Must saturate surface; insufficient pulse gives non-uniform coverage
H₂O pulse time	15–30 ms	Longer pulse needed on high-aspect-ratio textured surfaces
Purge time	3–8 s per half-cycle	Shorter purge risks CVD-mode growth; longer purge reduces throughput
Post-deposition anneal	350–450 °C, 15–30 min (forming gas or N₂)	Activates negative fixed charge and improves chemical passivation; essential for good Q_f
Resulting S_eff	< 5 cm/s	On p-type 1 Ω·cm Cz-Si after anneal; equivalent to J₀ < 5 fA/cm²

Process integration: In a PERC cell, the ALD Al₂O₃ layer is capped with a PECVD SiN_x layer (60–100 nm) that serves as a hydrogen source during contact firing and as a mechanical/chemical barrier. The Al₂O₃/SiN_x stack is then locally opened by laser ablation to form rear point contacts. For more details on ALD process optimization, see our ALD comprehensive guide.

2.5 Metallization

Front and rear contacts are formed by screen printing of Ag (front) and Al (rear) pastes, followed by a fast-firing step (700–800 °C peak, 1–3 s) that drives the Ag paste through the SiN_x ARC to contact the emitter and simultaneously sinters the rear Al contact. For advanced cell architectures (HJT, IBC), sputtered metal stacks (e.g., ITO/Ag or ITO/Cu by magnetron sputtering) replace screen printing to achieve finer line widths (< 30 μm vs. 40–60 μm for screen print) and lower contact resistance.

High-efficiency c-Si PERC solar cell fabrication flow — texturing, POCl3 emitter diffusion, SiNx ARC by PECVD, Al2O3 rear passivation by ALD, SiNx capping, and screen-print metallization with co-firing — Figure 1: High-Efficiency c-Si PERC Cell — Five-step fabrication flow (texturing → emitter diffusion → SiNx ARC → Al2O3/SiNx rear passivation → metallization) with representative process parameters and target metrics

3) Perovskite Solar Cell Fabrication

Metal halide perovskite solar cells (PSCs) have achieved certified efficiencies above 26% in single-junction and above 33% in tandem configurations. Unlike c-Si cells where the absorber is a bulk wafer, perovskite cells are entirely thin-film devices — every layer from electrode to absorber to transport layer is deposited, making plasma and thin-film processing central to the entire device.

3.1 Substrate Preparation and Bottom Electrode

The standard p-i-n (inverted) perovskite cell architecture is: glass/ITO/HTL/perovskite/ETL/metal. The process begins with substrate cleaning and bottom electrode deposition.

Plasma cleaning: Glass or flexible polymer substrates are cleaned in an O₂ plasma cleaner (100 W, 2–5 min, 200–500 mTorr) to remove organic contaminants and increase surface energy (water contact angle from > 60° to < 10°). This step is critical — poor substrate cleanliness is the leading cause of perovskite film pinholes and shunting.

ITO bottom electrode by sputtering: Indium tin oxide (In₂O₃:Sn, 90:10 wt%) is deposited by RF or DC magnetron sputtering from a ceramic ITO target. Typical parameters: 100–200 W DC power, 2–5 mTorr Ar pressure, 0–2% O₂ partial pressure (controls carrier concentration), room temperature to 200 °C substrate temperature. Target properties: sheet resistance 10–15 Ω/sq at 150 nm thickness, transmittance > 85% at 550 nm, resistivity < 3 × 10⁻⁴ Ω·cm.

3.2 ALD SnO₂ Electron Transport Layer

Tin dioxide (SnO₂) deposited by ALD is the preferred electron transport layer (ETL) for high-efficiency n-i-p perovskite cells due to its excellent conformality, precise thickness control, and low-temperature processing that is compatible with flexible substrates.

Parameter	Value	Notes
Precursors	TDMASn (tetrakis(dimethylamido)tin(IV)) / H₂O	TDMASn is preferred over SnCl₄ for lower temperature and Cl-free films
Substrate temperature	100–150 °C	Below 100 °C: incomplete reaction; above 200 °C: TDMASn decomposition
GPC	0.6–1.0 Å/cycle	~0.8 Å/cycle at 120 °C; slower than Al₂O₃ due to steric effects of TDMASn
Target thickness	15–25 nm	Thinner: pinholes cause shunting; thicker: increased series resistance
Number of cycles	190–310 cycles	For 15–25 nm target at 0.8 Å/cycle
Post-deposition treatment	UV-ozone, 15 min	Improves wettability for perovskite solution coating; optional if spin-coating immediately
Resulting properties	E_g ~ 3.6 eV, n ~ 2.0 (at 550 nm)	Wide bandgap ensures transparency; good electron extraction with CB alignment to perovskite

3.3 Perovskite Absorber Deposition

The perovskite absorber layer (typically methylammonium lead iodide CH₃NH₃PbI₃, formamidinium lead iodide FAPbI₃, or mixed-cation/mixed-halide compositions) can be deposited by several methods:

Spin coating (lab scale): One-step or two-step solution process using a spin coater. One-step: dissolve PbI₂ + MAI in DMF:DMSO (4:1), spin at 4000 rpm for 30 s with antisolvent drip (chlorobenzene or diethyl ether) at t = 15 s, anneal at 100 °C for 10 min. Two-step: spin-coat PbI₂ in DMF, dry, then dip in or spin-coat MAI in IPA solution. Typical film thickness: 400–600 nm.
Co-evaporation (scalable): Simultaneous thermal evaporation of PbI₂ and MAI (or FAI) from separate crucibles in high vacuum (< 10⁻⁵ Torr). Produces uniform, pinhole-free films over large areas. Substrate temperature: room temperature to 60 °C. Deposition rate: 0.5–2 Å/s per source, with real-time rate monitoring by QCM.
Hybrid vacuum-solution: Evaporate PbI₂ layer (200–300 nm), then convert by exposure to MAI vapor or solution — combines vacuum film quality with solution processing flexibility.

3.4 Top Electrode

The top electrode is typically a thin metal layer (Ag or Au, 80–120 nm) deposited by thermal evaporation through a shadow mask. For semi-transparent perovskite cells (used in tandem architectures), a sputtered ITO top electrode (50–80 nm) replaces the metal, requiring careful control of sputter damage to the underlying organic/perovskite layers. Buffer layers (SnO₂ by ALD, 10–20 nm, or MoO_x by evaporation, 5–10 nm) protect the perovskite from sputter damage during ITO deposition.

Perovskite solar cell n-i-p layer structure — glass/TCO substrate, ALD SnO2 electron transport layer, perovskite absorber, spin-coated hole transport layer, and evaporated back electrode with deposition methods and thicknesses — Figure 2: Perovskite Solar Cell — n-i-p layer structure from TCO substrate through ETL / absorber / HTL to back electrode, with deposition methods, thicknesses, and record PCE references (NREL 2025)

4) CIGS and CdTe Thin-Film Solar Cells

4.1 CIGS (Cu(In,Ga)Se₂) Absorber Deposition

CIGS thin-film cells use a polycrystalline chalcopyrite absorber with a tunable bandgap (1.0–1.7 eV depending on Ga/(In+Ga) ratio). The standard device structure is: glass/Mo/CIGS/CdS/ZnO/AZO/grid. Sputter deposition plays a central role.

Layer	Material	Deposition Method	Thickness	Key Parameters
Back contact	Mo	DC magnetron sputtering	500–1000 nm	Ar, 3–5 mTorr, 300–500 W; bilayer: high-pressure adhesion layer + low-pressure conductive layer; target R_sh < 0.5 Ω/sq
Absorber	Cu(In,Ga)Se₂	Co-sputtering of Cu, In, Ga targets + selenization	1.5–2.5 μm	Sputter metallic precursors at RT, then selenize in H₂Se or Se vapor at 500–550 °C for 30–60 min; alternative: co-evaporation of all elements at 550 °C
Buffer layer	CdS	Chemical bath deposition (CBD)	50–70 nm	CdSO₄/thiourea/NH₃, 60–80 °C, 8–12 min; alternative: ALD ZnOS or ZnMgO for Cd-free buffer
Window layer (i)	i-ZnO	RF magnetron sputtering	50–80 nm	ZnO target, Ar, 5–10 mTorr, 100–150 W RF; intrinsic (high resistivity) to prevent shunting
Window layer (TCO)	Al:ZnO (AZO)	DC/RF magnetron sputtering	200–400 nm	ZnO:Al₂O₃ (2 wt%) target, Ar, 2–5 mTorr, 200–400 W; R_sh < 20 Ω/sq, T > 80%
Grid	Ni/Al	E-beam evaporation or sputtering	50/2000 nm	Shadow mask or lift-off patterned

4.2 CdTe Solar Cells

CdTe cells use a simpler structure: glass/TCO/CdS/CdTe/back contact. The CdTe absorber (2–8 μm) is typically deposited by close-space sublimation (CSS) at 500–600 °C, though magnetron sputtering from a CdTe compound target is used in some production lines and R&D (RF sputtering, Ar, 5–10 mTorr, 100–200 W, 1–3 Å/s deposition rate, substrate temperature 200–350 °C). A critical activation step — CdCl₂ treatment at 380–420 °C for 20–30 min in air — recrystallizes the CdTe grain structure, promotes interdiffusion at the CdS/CdTe interface, and passivates grain boundaries. Without this step, cell efficiency drops by 5–10 percentage points absolute.

5) Tandem and Multi-Junction Solar Cells

5.1 Perovskite/Si Tandem Cells

Perovskite/silicon tandem cells hold the current certified efficiency record for two-terminal tandem devices (> 33%). The concept is straightforward: a wide-bandgap perovskite top cell (1.65–1.75 eV) absorbs high-energy photons while the silicon bottom cell (1.12 eV) absorbs the transmitted near-infrared light, reducing thermalization losses.

The critical interface between the two sub-cells is the recombination layer (also called the tunnel junction or interconnect layer), which must provide low-resistance ohmic contact for current matching while maintaining optical transparency. ALD-deposited layers are ideal for this function:

ALD SnO₂ (15–20 nm, deposited at 100 °C using TDMASn/H₂O): serves as both the electron transport layer for the perovskite and part of the recombination junction. Its precise thickness control by ALD ensures reproducible current matching.
Sputtered ITO (10–20 nm): provides lateral conductivity for current spreading between sub-cells. Must be deposited at low power (< 50 W RF) or with a buffer layer to avoid damaging the underlying silicon surface.
Sputtered NiO_x (10–20 nm, RF sputtering from NiO target in Ar, 50–100 W): hole transport layer for the perovskite top cell in p-i-n configuration. Alternatively, self-assembled monolayers (SAMs) like Me-4PACz are used in solution process.

5.2 Plasma Surface Activation for Wafer Bonding

For mechanically stacked tandem cells and III-V/Si multi-junction architectures, plasma surface activation enables direct wafer bonding at low temperatures. The process uses a brief O₂ or N₂ plasma treatment (50–200 W, 30–120 s, 200–500 mTorr) to activate the bonding surfaces by creating a high density of reactive hydroxyl (–OH) groups. The activated surfaces are then brought into contact at room temperature, forming initial van der Waals bonds that are strengthened by a low-temperature anneal (200–400 °C, 2–12 hours). This approach avoids the high-temperature processing (> 800 °C) that would degrade perovskite layers or introduce thermal mismatch stress in III-V/Si structures.

5.3 III-V Multi-Junction Cells

III-V multi-junction cells (GaInP/GaAs/Ge or GaInP/GaAs/GaInAs) achieve efficiencies above 47% under concentration. While the absorber layers are grown by MOCVD or MBE, thin-film and plasma processing steps are essential:

ARC deposition: Dual-layer MgF₂/ZnS or TiO₂/SiO₂ anti-reflection coatings by e-beam evaporation or sputtering.
Mesa isolation etch: ICP-RIE with BCl₃/Cl₂/Ar chemistry to define cell mesas with vertical sidewalls (500–800 W ICP, 50–150 W bias, 5–10 mTorr).
Contact layer etch: Selective removal of the GaAs cap layer after front metallization using RIE or wet etching (citric acid/H₂O₂).
ALD passivation: Al₂O₃ or AlN passivation of III-V surfaces (5–10 nm by ALD) to reduce surface recombination at mesa sidewalls.

Tandem solar cell architectures — 2-terminal perovskite/Si tandem with recombination layer, and III-V GaInP/GaAs/Ge triple-junction with tunnel junctions, showing carrier flow, polarity, and target PCE — Figure 3: Tandem & Multi-Junction Architectures — Perovskite/Si 2-terminal tandem (targeting >30% PCE) and III-V triple-junction (GaInP/GaAs/Ge, 44% under concentration) with tunnel junction coupling

6) Process Comparison: Deposition Methods for Solar Cell Layers

The following table summarizes the key thin-film deposition steps across all four solar cell technologies, with specific process parameters and the corresponding NineScrolls equipment.

Layer / Function	Material	Method	Thickness	Key Parameters	Cell Type
Anti-reflection coating	SiN_x:H	PECVD	75 nm	SiH₄/NH₃ 1:4, 300 °C, n=2.0, 8–10 nm/min	c-Si (PERC, TOPCon)
Rear passivation	Al₂O₃	ALD	10–15 nm	TMA/H₂O, 200 °C, 1.1 Å/cycle, anneal 400 °C	c-Si (PERC)
Rear passivation cap	SiN_x	PECVD	60–100 nm	SiH₄/NH₃, 300 °C, H source for firing	c-Si (PERC)
Tunnel oxide	SiO₂	Thermal / ALD	1.2–1.8 nm	Thermal: 600 °C dry O₂; ALD: BDEAS/O₃, 300 °C	c-Si (TOPCon)
Poly-Si cap	n⁺ a-Si:H	PECVD	100–200 nm	SiH₄/PH₃, 200–250 °C, 0.5–1.0 nm/s	c-Si (TOPCon)
Bottom electrode (TCO)	ITO	Sputtering	100–200 nm	DC/RF, 2–5 mTorr Ar, 0–2% O₂, R_sh < 15 Ω/sq	Perovskite, HJT, Tandem
Electron transport layer	SnO₂	ALD	15–25 nm	TDMASn/H₂O, 120 °C, 0.8 Å/cycle	Perovskite
Absorber	Perovskite	Spin coating / evaporation	400–600 nm	DMF:DMSO, 4000 rpm, antisolvent, anneal 100 °C	Perovskite
Back contact	Mo	DC sputtering	500–1000 nm	Ar, 3–5 mTorr, 300–500 W, bilayer for adhesion	CIGS
Absorber precursor	Cu-In-Ga	Co-sputtering	~1 μm (metallic)	Sequential or co-sputter, RT; then selenize 500–550 °C	CIGS
Window layer (TCO)	AZO	DC/RF sputtering	200–400 nm	ZnO:Al₂O₃ target, 2–5 mTorr, R_sh < 20 Ω/sq	CIGS, CdTe
Black silicon texture	Si (nanostructured)	ICP-RIE	500 nm features	SF₆/O₂, 2000 W ICP, 10 W bias, 20 mTorr, 10 min	mc-Si, HJT

Solar cell layer deposition method comparison matrix — SiNx ARC, Al2O3 passivation, ITO TCO, perovskite, and SnO2 ETL across PECVD, ALD/PEALD, sputter, evaporation, and solution processing — Figure 4: Solar Cell Layer Deposition — Method comparison matrix (PECVD / ALD / sputter / evaporation / solution) for each functional layer, highlighting the best-choice technique and common alternatives

7) Equipment Selection for Solar Cell Fabrication

Selecting the right processing equipment determines both the achievable cell efficiency and the process development timeline. The table below maps each solar cell processing step to the appropriate NineScrolls product, with guidance on what to look for in each system.

Process Step	NineScrolls Product	Why This System	Key Specs to Verify
SiN_x ARC + passivation, a-Si:H for HJT/TOPCon, SiO_x interlayers	PECVD Systems	13.56 MHz RF for high H content; precise gas ratio control for n=2.0 targeting; 300 °C capable	Gas mixing accuracy (SiH₄/NH₃ ratio), temperature uniformity (± 2 °C), deposition rate control
Al₂O₃ rear passivation, SnO₂ ETL, tunnel oxide, interface layers	ALD Systems	Self-limiting chemistry ensures conformal coverage on textured Si; sub-nm thickness control for tunnel oxide	GPC uniformity (< 2%), precursor delivery consistency, temperature range (100–300 °C)
ITO/AZO/FTO electrodes, Mo back contact, CIGS/CdTe absorber precursors, metal contacts	Sputter Systems	DC and RF capable; multi-target for sequential or co-sputtering; reactive sputtering for oxide TCOs	Target-to-substrate distance, O₂ partial pressure control, substrate rotation for uniformity
Black silicon nanostructuring, mesa isolation for III-V cells	ICP Etcher Series	Independent ICP source and bias control allows low-damage nanostructuring at high plasma density	Minimum achievable bias power (should reach < 10 W), SF₆/O₂ gas compatibility
Edge isolation, selective emitter patterning, contact layer removal	RIE Etcher Series	Cost-effective for standard etch steps that do not require high plasma density	Fluorine and chlorine gas compatibility, endpoint detection
Substrate cleaning, surface activation for bonding, wettability improvement	Plasma Cleaners	Simple O₂/Ar/N₂ plasma for organic removal and surface activation; benchtop form factor	Power range (50–300 W), gas flexibility (O₂, Ar, N₂), chamber size for wafer handling
Quick-turnaround etching for patterning, PR descum, thin-film etching	Compact RIE	Small footprint for solar R&D labs; adequate for non-critical etch steps	Gas compatibility (O₂, CF₄, Ar), power range, chamber size
Perovskite spin coating, photoresist patterning for cell definition	Coater/Developer	Programmable spin speed profiles for antisolvent drip timing; N₂ glovebox compatible	Speed range (500–6000 rpm), acceleration control, programmable dispense timing
Photoresist stripping, post-etch polymer removal	Striper Systems	Solvent-based or dry stripping for clean surface preparation between process steps	Chemical compatibility, rinse/dry capability, throughput

8) Quality Control and Film Characterization

Solar cell thin films require characterization of optical, electrical, and structural properties. The following measurement techniques map directly to process control parameters.

8.1 Optical Properties (n, k, Thickness)

Spectroscopic ellipsometry is the primary tool for characterizing SiN_x ARC and Al₂O₃ passivation layers. Key measurements:

Refractive index (n): Target n = 2.0 ± 0.02 at 632 nm for SiN_x ARC. n > 2.05 indicates Si-rich film (higher absorption, potentially better passivation); n < 1.95 indicates N-rich film (poorer passivation, weaker absorption). For Al₂O₃, target n = 1.65 ± 0.02 at 632 nm.
Extinction coefficient (k): k should be < 0.001 at 600 nm for SiN_x ARC to minimize parasitic absorption. k > 0.01 indicates excessive Si-rich composition — reduce SiH₄/NH₃ ratio.
Thickness: Uniformity target < ± 2% across wafer. For SiN_x: 75 ± 2 nm; for Al₂O₃: 12 ± 1 nm.

8.2 Minority Carrier Lifetime

Photoconductance decay (PCD) measurement (e.g., Sinton WCT-120) is the most direct quality metric for passivation layers:

After SiN_x deposition (as-deposited): τ_eff > 50 μs on 1 Ω·cm p-type Cz-Si indicates adequate chemical passivation.
After contact firing (post-firing): τ_eff > 200 μs confirms hydrogen activation and bulk passivation. Drop in lifetime after firing suggests insufficient H content or firing temperature too high.
After ALD Al₂O₃ + anneal: τ_eff > 1 ms on 1 Ω·cm p-type Cz-Si; implied J₀ < 5 fA/cm². This is the benchmark for high-quality PERC rear passivation.

8.3 Sheet Resistance and Electrical Properties

Four-point probe: ITO sheet resistance target: 10–15 Ω/sq at 150 nm; AZO: < 20 Ω/sq at 300 nm; Mo back contact: < 0.5 Ω/sq at 800 nm. Map sheet resistance at 9+ points across wafer for uniformity assessment.
Hall effect measurement: Carrier concentration and mobility of TCO films. ITO target: n_e ~ 5 × 10²⁰ cm⁻³, mobility > 30 cm²/V·s.
Contact resistance (TLM): Specific contact resistance < 5 mΩ·cm² for screen-printed Ag on n⁺ emitter; < 1 mΩ·cm² for sputtered contacts.

8.4 Structural and Compositional Analysis

FTIR: Si-N and N-H bond peak ratios in SiN_x correlate with refractive index and hydrogen content. N-H stretch at 3340 cm⁻¹ and Si-N stretch at 840 cm⁻¹ are the primary diagnostic peaks.
XRD: Perovskite crystallinity and phase purity; CIGS chalcopyrite phase confirmation; preferred orientation of sputtered Mo and TCO films.
SEM/AFM: Surface morphology of textured Si (pyramid height and coverage), black silicon nanostructure dimensions, perovskite grain size (target > 200 nm for low recombination).

9) Troubleshooting Guide

Problem	Likely Cause	Diagnostic	Solution
SiN_x ARC appears blue instead of dark blue/purple (n too low)	SiH₄/NH₃ ratio too low (N-rich film); gas line contamination reducing SiH₄ flow	Ellipsometry: check n at 632 nm (expect < 1.95); FTIR: weak Si-H peak	Increase SiH₄/NH₃ ratio by 10–15%; verify MFC calibration for SiH₄; check for SiH₄ line pressure drop
Low minority carrier lifetime after ALD Al₂O₃ (< 100 μs)	Insufficient post-deposition anneal; surface contamination before ALD; pinholes in film	Compare as-deposited vs. annealed lifetime; TEM for pinholes; XPS for interface contamination	Verify anneal at 400 °C for 20+ min in forming gas; clean wafers immediately before ALD (HF dip + DI rinse); increase film thickness to 15 nm; extend TMA/H₂O pulse times
Non-uniform black silicon texture (center-to-edge variation)	Gas distribution non-uniformity in ICP chamber; temperature gradient across wafer chuck	SEM at center, mid-radius, and edge; check He backside cooling uniformity	Adjust gas injection pattern; verify wafer clamping force; increase chamber pressure slightly (20 to 30 mTorr) to improve uniformity at cost of directionality
High series resistance in perovskite cell (fill factor < 70%)	ITO sheet resistance too high; SnO₂ ETL too thick; poor perovskite/ETL interface	Four-point probe ITO R_sh; cross-section SEM for layer thicknesses; J-V curve shape analysis	Increase ITO thickness or O₂ partial pressure; reduce SnO₂ ALD cycles (target 15–20 nm); improve substrate cleaning before SnO₂ deposition
CIGS cell shunting (low R_sh, poor V_oc)	Pinholes in CdS buffer layer; Na diffusion from glass through Mo creating conductive paths	Dark J-V curve for shunt resistance; EBIC imaging for shunt locations; EDS for Na at grain boundaries	Increase CdS CBD time to 12 min for complete coverage; use Na barrier layer (SiO₂ or SiN_x by PECVD, 100–200 nm) on glass before Mo deposition; check Mo bilayer integrity
Perovskite film pinholes and poor coverage	Poor substrate wettability; antisolvent timing off; ambient humidity too high	Optical microscopy (bright spots = pinholes); contact angle measurement on substrate	O₂ plasma clean substrate for 3–5 min before coating; adjust antisolvent drip to t = 12–15 s; process in N₂ glovebox (H₂O < 1 ppm)
Sputtered ITO high resistivity (> 5 × 10⁻⁴ Ω·cm)	O₂ partial pressure too high (over-oxidized); target poisoned; substrate temperature too low	Hall effect: check carrier concentration (should be > 3 × 10²⁰ cm⁻³) and mobility (> 20 cm²/V·s)	Reduce O₂ flow by 0.5 sccm increments; condition target with 5 min pre-sputter in pure Ar; increase substrate temp to 150–200 °C
Tandem cell current mismatch (J_sc lower than expected)	Perovskite bandgap wrong (too high or too low); intermediate layer too absorbing; ARC not optimized for tandem	EQE measurement of each sub-cell; reflectance spectrum of tandem stack	Tune perovskite composition for E_g = 1.68 eV; reduce ITO interlayer thickness to minimize parasitic absorption; design ARC for tandem spectrum (may need dual-layer MgF₂/ZnS)

10) Conclusion

Solar cell fabrication — whether crystalline silicon, perovskite, CIGS, CdTe, or tandem — is fundamentally defined by thin-film and plasma processing quality. The difference between a laboratory champion cell and a production dud is almost never the absorber material itself but the precision of the passivation layers, anti-reflection coatings, electrodes, and interfaces deposited around it. PECVD SiN_x at the right refractive index, ALD Al₂O₃ at the right thickness, sputtered ITO at the right resistivity, and properly activated surfaces for bonding — these are the processes that separate high efficiency from mediocre performance.

The process parameters in this guide are not theoretical targets but working recipes that can be implemented on standard research-grade equipment. Start with the baseline parameters, verify with the quality control methods described, and iterate using the troubleshooting table when results deviate from specification.

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Frequently Asked Questions

What is the most critical thin-film process step for crystalline silicon solar cell efficiency?

The PECVD SiN_x:H anti-reflection and passivation coating has the single largest impact on c-Si cell efficiency. A properly optimized SiN_x film (n = 2.0, 75 nm, high hydrogen content) simultaneously reduces front-surface reflectance from ~11% to < 2%, passivates surface dangling bonds (reducing surface recombination velocity from > 10⁴ cm/s to < 10 cm/s), and provides hydrogen for bulk defect passivation during contact firing. Getting the SiH₄/NH₃ gas ratio right (typically 1:4 for n = 2.0 at 300 °C) is the single most important process parameter. A cell with perfect SiN_x can gain 1.5–2.5% absolute efficiency over one with a mediocre coating.

Can I use the same ALD system for both Al₂O₃ passivation on c-Si and SnO₂ ETL for perovskite cells?

Yes. Both processes use thermal ALD in overlapping temperature ranges (Al₂O₃ at 200 °C, SnO₂ at 100–150 °C), and a single ALD reactor with appropriate precursor delivery lines (TMA and TDMASn bubblers, H₂O source) can handle both. The key consideration is cross-contamination: run a chamber conditioning cycle (10–20 cycles of the new process) when switching between Al and Sn chemistries, and use dedicated precursor lines rather than shared manifolds. For labs doing both c-Si and perovskite research, a single ALD system with multi-precursor capability is the most cost-effective investment.

What equipment do I need to start a perovskite/Si tandem cell R&D line?

A minimum viable perovskite/Si tandem R&D line requires five core tools: (1) a PECVD system for SiN_x ARC and a-Si:H interlayers on the silicon bottom cell; (2) an ALD system for Al₂O₃ rear passivation and SnO₂ electron transport layer; (3) a sputter system for ITO electrodes (both the recombination interlayer and semi-transparent top contact); (4) a spin coater (ideally in an N₂ glovebox) for perovskite absorber deposition; and (5) a plasma cleaner for substrate preparation and optional surface activation for bonding steps. An ICP-RIE system is needed if you plan to use black silicon texturing instead of conventional KOH wet etching. This equipment set covers the full process flow from silicon bottom cell to perovskite top cell to final device characterization.

References

Green, M. A. Solar Cells: Operating Principles, Technology and System Applications. Prentice Hall (1982). ISBN 978-0138222703.
NREL Best Research-Cell Efficiency Chart. nrel.gov/pv/cell-efficiency.html
Green, M. A., et al. “Solar cell efficiency tables (version 64).” Progress in Photovoltaics: Research and Applications, 32(7), 425–441 (2024). doi:10.1002/pip.3831
Dingemans, G. & Kessels, W. M. M. “Status and prospects of Al₂O₃-based surface passivation schemes for silicon solar cells.” Journal of Vacuum Science & Technology A, 30(4), 040802 (2012). doi:10.1116/1.4728205
Otto, M., et al. “Black silicon photovoltaics.” Advanced Optical Materials, 3(2), 147–164 (2015). doi:10.1002/adom.201400395
Al-Ashouri, A., et al. “Monolithic perovskite/silicon tandem solar cell with >29% efficiency by enhanced hole extraction.” Science, 370(6522), 1300–1309 (2020). doi:10.1126/science.abd4016
Repins, I., et al. “19.9%-efficient ZnO/CdS/CuInGaSe₂ solar cell with 81.2% fill factor.” Progress in Photovoltaics: Research and Applications, 16(3), 235–239 (2008). doi:10.1002/pip.822
Baena, J. P. C., et al. “Highly efficient planar perovskite solar cells through band alignment engineering.” Energy & Environmental Science, 8(10), 2928–2934 (2015). doi:10.1039/C5EE02608C