imec, KU Leuven, Samsung, and Lam Research Detail a Monolithically Stackable Oxide-Semiconductor 3D-DRAM Cell in New July 2026 Paper

By NineScrolls Team · 2026-07-27 · 4 min read · Industry

What Happened

On July 21, 2026, Semiconductor Engineering highlighted a technical paper from imec, KU Leuven, Samsung Electronics, and Lam Research titled "Optimization of 3D-DRAM Architecture with Oxide-Semiconductor Channel through Process and Device Simulation," published in the IEEE Journal of the Electron Devices Society (doi: 10.1109/JEDS.2026.3715074).

The authors investigate a monolithically stackable 3D-DRAM cell built on an oxide-semiconductor channel (OSC), using an integrated framework that combines process emulation, TCAD device simulation, parasitic extraction, and analytical modeling. In plain terms: they modeled both how the cell would be fabricated and how it would behave electrically, then optimized the architecture against both constraints at once.

The presence of Lam Research — an etch and deposition equipment supplier — alongside imec and a memory maker is the tell. This is not a purely academic device study; it is a process-aware architecture optimization aimed at what a fab would actually have to build.

Why an Oxide-Semiconductor Channel

Planar DRAM scaling is running into a wall, and the industry's answer is to go vertical — stacking cells the way 3D NAND stacked flash. The complication is that DRAM's access transistor must hold charge with extremely low leakage, and conventional silicon channels leak too much as dimensions shrink.

Oxide semiconductors such as IGZO (indium-gallium-zinc-oxide) offer extremely low off-state leakage, useful mobility, and — critically — low-temperature processing that is compatible with back-end-of-line integration. That last property is what makes monolithic stacking of individual cells feasible, opening a path to low-power, high-density 3D-DRAM.

The Process Stack Behind a Vertical 3D-DRAM Cell

A vertical OSC-based DRAM cell is only as good as the deposition and etch steps that form it. The oxide-semiconductor channel has to be laid down as an ultra-thin, conformal film inside deep, narrow vertical structures — a job that falls to atomic layer deposition (ALD), where imec has already demonstrated functional transistors with sub-10nm conformally deposited IGZO channels.

Gate dielectrics and storage nodes add further ALD and plasma-enhanced deposition steps, each of which must maintain uniform thickness and composition down the full height of the stack. Every monolayer of variation matters at these dimensions, which is precisely why a process-emulation-plus-TCAD approach is valuable: it lets designers see how a real deposition or etch profile translates into device performance before committing to silicon.

The High-Aspect-Ratio Etch Problem

Before anything can be deposited, the vertical features themselves have to be etched. The move toward fully 3D DRAM is pushing aspect ratios from the ranges familiar in today's capacitor trenches toward the 100:1 and eventually 200:1 territory associated with the most aggressive 3D memory. Forming those channels demands deep, anisotropic, damage-controlled plasma etching with tight sidewall-profile and uniformity control from top to bottom of the feature.

This is the domain of high-density inductively coupled plasma etching. Readers who want the fundamentals can review our guides on deep reactive ion etching and the Bosch process and on ICP-RIE technology for advanced etching, which explain why high plasma density and independent bias control are what make high-aspect-ratio, low-damage etching possible. For a broader primer, our reactive ion etching guide covers the underlying mechanisms.

NineScrolls Niche Angle

For the plasma-processing and thin-film community, this paper is a reminder that 3D-DRAM is fundamentally an etch-and-deposition problem dressed up as a device problem. Two capabilities sit on the critical path: high-aspect-ratio ICP/DRIE etch to open the vertical channels, and conformal ALD (plus PECVD) to line them with oxide-semiconductor channel, gate dielectric, and storage films. Both must hold uniformity across features far taller than they are wide.

For the equipment supply chain, Lam Research's co-authorship signals that tool vendors are already co-designing processes with foundries and research institutes at the simulation stage — plasma sources, gas delivery, and process monitoring all have to be qualified for these extreme geometries long before volume tools ship. Labs and R&D groups working on oxide-semiconductor transistors, vertical memory test structures, or high-aspect-ratio etch development are exactly the users NineScrolls serves, and the etch fundamentals above — ICP-RIE and deep reactive ion etching — are the starting point for building those structures.