Nanofabrication Techniques: Building the Nanoscale Future

By NineScrolls Engineering · 2024-01-08 · 22 min read · Nanotechnology

Target Readers: Nanofabrication engineers, e-beam lithography users, process integration engineers, and researchers building nanostructures for photonics, quantum devices, NEMS, or biosensors. This guide provides specific resist recipes, etch parameters, and metallization processes tested at the sub-100 nm scale.

Introduction: From Pattern to Nanostructure

Nanofabrication is the sequential transfer of a pattern into a functional nanostructure — and every step in that sequence has parameters that determine whether you get a publishable device or a featureless wafer. A paper reporting "50 nm lines were patterned by EBL and etched by RIE" omits the details that actually matter: which resist, what dose, what developer concentration, what etch chemistry, what pressure, what power, and what selectivity was achieved.

This guide provides those details. We cover the complete nanofabrication workflow from resist coating through pattern transfer, metallization, and multi-level integration, with specific process parameters for each step. Where relevant, we reference our companion guides on reactive ion etching fundamentals, atomic layer etching for ultimate precision, and ALD thin film deposition for deeper dives into individual process modules.

1) E-Beam Resist Selection and Dose Optimization

The resist is the first critical decision in any nanofabrication process. E-beam resists differ fundamentally from optical photoresists: they must balance resolution, sensitivity, etch resistance, and process compatibility. The wrong resist choice can limit your resolution regardless of how good your e-beam column is.

1.1 E-Beam Resist Comparison

The following table summarizes the most widely used e-beam resists and their practical characteristics. Sensitivity values are for 100 kV acceleration; scale by approximately 1.5× for 30 kV systems.

1.2 Coating and Bake Parameters

Resist thickness is controlled by spin speed and solution concentration. For nanoscale patterning, thinner films generally give better resolution because they reduce forward scattering and improve aspect ratio control. However, the film must be thick enough to survive subsequent etch or liftoff steps.

Standard PMMA coating process:

• Substrate pre-clean: O₂ plasma, 100 W, 30 s (removes organic residue and improves adhesion)
• Spin: PMMA 950K A4 at 4000 rpm, 60 s → ~200 nm thickness
• For thinner film (~100 nm): PMMA 950K A2 at 4000 rpm
• Pre-bake: 180°C hotplate, 5 min (drives off anisole solvent)
• Cool to room temperature before loading into e-beam

HSQ (XR-1541) coating process:

• Substrate: freshly cleaned, no HMDS (HSQ is inorganic)
• Spin: XR-1541-006 (6% solids) at 4000 rpm → ~90 nm; at 1500 rpm → ~180 nm
• Pre-bake: 80°C hotplate, 4 min (higher temperatures cause premature crosslinking)
• Expose within 4 hours — HSQ ages and loses sensitivity after coating

1.3 Dose Optimization and Proximity Effect Correction

The optimal dose depends on resist type, acceleration voltage, substrate material, pattern density, and feature size. Dense patterns require lower doses than isolated features because backscattered electrons from adjacent patterns contribute additional exposure (the proximity effect).

Practical dose test procedure:

1. Write a dose matrix with the target pattern at doses spanning 0.5× to 2× the nominal value
2. Include both isolated and dense features at each dose
3. Develop and inspect by SEM — optimal dose shows complete clearing (positive) or full crosslinking (negative) without overexposure
4. Measure CD vs. dose to find the process latitude (dose range giving acceptable CD)

Proximity effect correction (PEC) basics:

• Backscatter coefficient η depends on substrate (Si: η ≈ 0.7 at 100 kV; GaAs: η ≈ 0.9; light substrates like SiN membranes: η ≈ 0.05)
• Backscatter range at 100 kV on Si: ~30 µm — features within this radius affect each other
• Software PEC modulates dose across the pattern: edges of large features receive higher dose, centers receive lower
• For simple layouts, manual bias (sizing features ±10–20% to compensate) may suffice
• At 30 kV, the backscatter range shrinks to ~3 µm, reducing proximity effects but increasing forward scattering

1.4 Development Recipes

2) Pattern Transfer by Plasma Etching

Once the resist pattern is developed, it must be transferred into the underlying substrate or thin film. Plasma etching — specifically reactive ion etching (RIE) and ICP-RIE — is the primary method for anisotropic pattern transfer at the nanoscale. The challenge at sub-100 nm dimensions is maintaining sidewall verticality, minimizing line edge roughness (LER), and achieving sufficient selectivity to the resist mask.

2.1 Nanoscale Etch Recipes by Material

The following recipes are starting points for sub-100 nm feature etching. All pressures are in mTorr, flows in sccm, and powers in watts. Etch rates and selectivities are approximate and depend on chamber condition, loading, and feature geometry.

Silicon etching (nanowires, fins, photonic crystals):

SiO₂ etching (hardmask opening, contact holes):

• Chemistry: CHF₃ 25 sccm / Ar 25 sccm (or C₄F₈ 10 / Ar 30 for higher selectivity to Si)
• ICP power: 400–600 W; RF bias: 50–100 W
• Pressure: 5–10 mTorr
• SiO₂ etch rate: 80–150 nm/min
• Selectivity to Si: 10–15:1 (CHF₃/Ar); 20–40:1 (C₄F₈/Ar)
• Selectivity to PMMA: ~1:1 — use HSQ or hardmask for deep oxide etching

Metal etching (Cr, Al, Ti hardmasks):

• Cr: Cl₂ 30 / O₂ 5 sccm, ICP 400 W, bias 50 W, 5 mTorr → ~20 nm/min; excellent etch mask for Si
• Al: BCl₃ 30 / Cl₂ 15 sccm, ICP 500 W, bias 30 W, 5 mTorr → ~100 nm/min
• Ti: Cl₂ 30 / Ar 10 sccm, ICP 500 W, bias 40 W, 5 mTorr → ~30 nm/min
• For noble metals (Au, Pt) that do not form volatile halides: use ion beam etching (IBE) with Ar, 300–500 eV, 1 mA/cm² → ~10–20 nm/min

Polymer and organic film etching (resist descum, planarization layer removal):

• O₂ plasma: 50 sccm O₂, 100–200 W RF, 50–100 mTorr → 100–300 nm/min
• O₂/CF₄ (95:5): adds fluorine passivation for directional polymer etch → improved sidewall verticality
• For resist descum (removing thin residual resist in developed areas): O₂, 50 W, 10 s — removes ~5–10 nm

2.2 Hardmask Strategies for Deep Nanoscale Etching

When resist selectivity is insufficient for the required etch depth, a hardmask layer is inserted between resist and substrate. The fabrication sequence becomes: deposit hardmask → coat resist → e-beam pattern → etch hardmask → strip resist → etch substrate through hardmask → remove hardmask.

• SiO₂ hardmask: 20–50 nm deposited by PECVD (SiH₄/N₂O, 300°C) or sputtered; patterned with CHF₃/Ar; selectivity to Si > 10:1 in Cl₂/HBr
• Cr hardmask: 15–30 nm by sputtering; patterned with Cl₂/O₂ plasma; selectivity to Si > 20:1 in SF₆; removal by Cr wet etch (ceric ammonium nitrate)
• Al₂O₃ hardmask: 5–20 nm by ALD (TMA/H₂O at 200°C); extremely conformal and pinhole-free; patterned with BCl₃/Cl₂; selectivity to Si > 30:1
• HSQ (as hardmask): After e-beam exposure and development, crosslinked HSQ behaves as SiO₂ — no additional deposition step needed; selectivity to Si ~5–8:1 in Cl₂/HBr

2.3 Achieving Low Line Edge Roughness

Line edge roughness (LER) at the nanoscale is a composite of resist LER and etch-transferred LER. For sub-50 nm features, 3σ LER below 3 nm is typically required. Key strategies:

• Resist choice: HSQ gives the lowest LER (~1–2 nm 3σ) because it converts to amorphous SiO₂ with no grain structure; ZEP gives ~2–3 nm; PMMA gives ~4–6 nm
• Cold development: Developing PMMA in cold MIBK:IPA (0–5°C) reduces LER by ~30% compared to room-temperature development
• Etch smoothing: Adding a small O₂ flow (2–5 sccm) to Cl₂-based Si etch can form a thin sidewall oxide that smooths LER during pattern transfer
• Low bias power: Reducing RF bias below 20 W decreases ion-induced roughening at the cost of lower etch rate

3) Liftoff Metallization for Nanostructures

Liftoff is the preferred method for patterning metals that cannot be plasma-etched (Au, Pt, and complex stacks like Ti/Au or Cr/Au). The process deposits metal over a patterned resist, then dissolves the resist to "lift off" metal from unwanted areas, leaving metal only where the resist had openings.

3.1 Resist Profile Requirements

Successful liftoff requires an undercut resist profile so that the deposited metal film breaks cleanly at the resist sidewall. A vertical or re-entrant (overhanging) profile ensures discontinuity between the metal on top of the resist and the metal on the substrate.

PMMA/MMA bilayer liftoff process:

1. Spin MMA(8.5)MAA EL-11 at 4000 rpm → ~400 nm copolymer layer; bake 150°C, 5 min
2. Spin PMMA 950K A4 at 4000 rpm → ~200 nm top layer; bake 180°C, 5 min
3. E-beam expose at 250–350 µC/cm² (100 kV) — both layers are positive-tone
4. Develop in MIBK:IPA 1:3, 90 s — the MMA layer has higher sensitivity, creating the undercut
5. Inspect undercut by cross-section SEM: target 100–200 nm lateral undercut per side

PMMA/LOR bilayer (alternative for larger features):

• Spin LOR-3A at 3000 rpm → ~300 nm; bake 170°C, 5 min
• Spin PMMA 950K A4 at 4000 rpm; bake 180°C, 5 min
• Expose and develop PMMA normally — LOR is not e-beam sensitive
• Etch LOR through PMMA openings with MF-CD-26 (TMAH), 30–60 s, to create undercut
• LOR undercut is independently tunable by etch time

3.2 Metal Deposition for Liftoff

E-beam evaporation is strongly preferred over sputtering for liftoff because evaporation produces directional deposition (line-of-sight), keeping the resist sidewalls clear of metal. Sputtering is conformal and coats the sidewalls, causing liftoff failure.

Common metal stacks for nanodevices:

• Ohmic contacts to Si: Ti (5 nm) / Au (50–100 nm) — Ti adhesion layer prevents Au delamination
• Ohmic contacts to III-V: Ni (10 nm) / Ge (30 nm) / Au (60 nm) for GaAs; Ti (10 nm) / Al (100 nm) for GaN
• Plasmonic structures: Cr (2 nm) / Au (30–50 nm) — thin Cr minimizes optical damping
• Magnetic structures: Ti (3 nm) / Co (20–40 nm) / Au (5 nm cap)
• Superconducting devices: Al (30–80 nm) or NbN (by reactive sputtering, not compatible with standard liftoff)

Deposition parameters:

• Base pressure: < 5 × 10⁻⁷ Torr before starting evaporation
• Deposition rate: 0.5–2 Å/s (slower rates give denser, smoother films)
• Maximum total metal thickness: approximately 1/3 of resist thickness to ensure clean break
• Substrate tilt/rotation: tilt at 0° (normal incidence) for sharpest liftoff edges; angled deposition creates shadow effects useful for Dolan bridge junctions

3.3 Liftoff Procedure

• Soak in warm acetone (50–60°C) or NMP (N-methyl-2-pyrrolidone at 70–80°C) for 30–60 min
• Gentle ultrasonic agitation (low power, short bursts) — avoid high power on delicate nanostructures
• If resist remains: spray with acetone from a squeeze bottle while in the solvent bath
• Rinse: IPA, then DI water; blow dry with N₂
• Inspect by optical microscope and SEM for incomplete liftoff, re-deposition, or edge burrs

4) Nanoimprint Lithography

Nanoimprint lithography (NIL) transfers patterns by physically deforming a resist using a pre-patterned template (mold), achieving sub-10 nm resolution without the diffraction limits of optical lithography or the throughput constraints of e-beam. Two primary variants are used: thermal NIL (T-NIL) and UV-NIL.

4.1 Thermal NIL vs. UV-NIL Process Comparison

4.2 Template Fabrication

The template (mold) contains the inverse of the target pattern and is typically fabricated by e-beam lithography on a Si or quartz substrate followed by plasma etching. Template quality directly determines imprint quality.

• Template etch: HSQ resist on Si template; etch with Cl₂/HBr ICP-RIE (see Section 2.1); target depth = desired feature height + 20% overetch margin
• Anti-stick coating: Vapor-phase F₁₃-OTCS (tridecafluoro-1,1,2,2-tetrahydrooctyltrichlorosilane) or FDTS; deposit in vacuum desiccator, 1 hour at 150°C — reduces surface energy from ~60 mJ/m² to < 15 mJ/m²
• Template lifetime: > 100 imprints with proper anti-stick coating and cleaning protocol
• Cleaning between imprints: O₂ plasma, 200 W, 5 min; re-apply anti-stick coating every 20–50 imprints

4.3 Residual Layer Removal

After imprinting, a thin residual layer of resist remains at the bottom of all features. This must be removed by a short plasma etch (breakthrough etch) before the pattern can be transferred into the substrate.

• O₂ RIE: 20 sccm O₂, 50–100 W RF, 50 mTorr, 10–30 s (for organic resists)
• CHF₃/O₂: for sol-gel or hybrid resists with inorganic content
• Target: complete removal of residual layer without significant lateral erosion of feature edges
• Monitor by SEM cross-section or etch rate calibration on unpatterned witness sample

5) Self-Assembly for Sub-20 nm Features

When feature sizes drop below 20 nm, both e-beam lithography throughput and resist-based pattern fidelity become limiting. Self-assembly techniques — particularly block copolymer directed self-assembly (DSA) and self-assembled monolayers (SAMs) — offer a path to dense, periodic nanostructures at scales that are impractical by conventional lithography.

5.1 Block Copolymer Directed Self-Assembly (DSA)

Principle: Diblock copolymers (e.g., PS-b-PMMA) spontaneously phase-separate into periodic domains whose size (L₀) is determined by the molecular weight. By confining the copolymer in lithographically defined templates (chemo-epitaxy or grapho-epitaxy), the self-assembled domains align with the template pattern, multiplying the pattern density by 2× to 10×.

PS-b-PMMA DSA process recipe:

1. Neutral brush layer: Spin PS-r-PMMA random copolymer (58% PS), 2000 rpm; anneal 250°C in N₂, 5 min to graft; rinse ungrafted polymer with toluene
2. Guide pattern: E-beam or DUV lithography to define guiding lines (width ≈ 0.5–0.7 L₀) at pitch = n × L₀ (density multiplication factor n = 2–4)
3. BCP coating: Spin PS-b-PMMA (e.g., 67K-b-67K for L₀ ≈ 40 nm; 25K-b-25K for L₀ ≈ 22 nm) at 3000 rpm; film thickness ≈ 1.0–1.5 × L₀
4. Thermal annealing: 250°C in N₂, 5–15 min for complete ordering; or solvent vapor anneal with THF/toluene (60°C, 30 min) for lower temperature budget
5. PMMA removal: UV flood exposure (254 nm, 10 J/cm²) crosslinks PS and degrades PMMA; develop in acetic acid 3–5 min to remove PMMA domains, leaving PS template
6. Pattern transfer: O₂ RIE (50 W, 5 mTorr, 15 s) to etch through remaining PS into underlying hardmask or substrate

High-χ BCPs for sub-10 nm: PS-b-PDMS (χ ≈ 0.26 vs. 0.04 for PS-b-PMMA) achieves L₀ < 15 nm. After anneal, CF₄ RIE removes PDMS surface wetting layer; O₂ RIE then selectively removes PS, leaving oxidized PDMS (SiO₂-like) as an etch mask with selectivity > 10:1 to organic underlayers.

5.2 Self-Assembled Monolayers (SAMs)

SAMs are single-molecule-thick organic films that spontaneously form ordered arrays on surfaces. In nanofabrication, SAMs serve as:

• Area-selective deposition (ASD) blockers: Octadecylphosphonic acid (ODPA) SAMs on metal oxide surfaces block ALD nucleation, enabling selective deposition on adjacent Si or metal regions without lithography
• Surface energy modifiers: Fluorinated SAMs reduce surface energy for NIL anti-stick coatings; amino-terminated SAMs (APTES) promote adhesion for biosensor functionalization
• Etch masks: Microcontact-printed SAMs define hydrophobic/hydrophilic patterns for selective wet etching of metals (10–20 nm resolution limited by stamp deformation)

Typical SAM deposition:

• Substrate cleaning: UV/ozone 15 min or O₂ plasma 100 W, 2 min
• Thiol SAM on Au: immerse in 1–5 mM alkanethiol in ethanol, 12–24 hours at RT
• Silane SAM on SiO₂: vapor-phase OTS or HMDS in vacuum desiccator at 120°C, 1 hour; or solution-phase in toluene, 1 hour
• Phosphonic acid SAM on Al₂O₃/HfO₂: 1 mM ODPA in ethanol, 60°C, 30 min; anneal 140°C, 10 min

6) Multi-Level Nanofabrication

Real nanodevices — quantum dot arrays, photonic crystal circuits, NEMS resonators — require multiple patterned layers with precise registration. Each additional level compounds alignment challenges, planarity requirements, and thermal budget constraints.

6.1 Overlay Alignment

Alignment mark design:

• First-level (global) marks: large crosses or vernier patterns (50–200 µm) etched into the substrate at layer 1; must survive all subsequent processing
• Material: etch marks into Si (200–500 nm deep) or deposit high-contrast metal marks (Cr, Au) — metal marks give better visibility in e-beam but may need to be placed outside the active device area
• Placement: 4 marks near wafer/chip edges for global alignment (translation + rotation + magnification correction); additional local marks near each write field for field-level correction

Achievable overlay accuracy:

• E-beam (global alignment only): ±50–200 nm
• E-beam (global + local field alignment): ±10–30 nm
• UV-NIL (moiré-based alignment): ±50–100 nm
• EUV / DUV stepper: ±1–5 nm (production tools)

6.2 Planarization Between Levels

Topography from previous patterning levels degrades resist coating uniformity and causes depth-of-focus problems in subsequent lithography. Planarization options for R&D nanofabrication:

• Spin-on dielectric (SOD): HSQ (FOx-16) or spin-on glass (SOG) — spin at 2000–4000 rpm, cure at 350–400°C in N₂; provides reasonable planarization for features < 1 µm pitch
• PECVD SiO₂: Conformal deposition followed by resist-etchback (blanket RIE with CHF₃/Ar until surface is flat); good for isolated features but poor for large-area topography
• ALD planarization: Thin ALD Al₂O₃ or SiO₂ (5–20 nm) provides conformal fill of narrow trenches; combined with resist etchback for surface leveling
• CMP (chemical-mechanical polishing): Best planarization but requires dedicated equipment; removes topography to < 1 nm RMS over mm-scale areas

6.3 Thermal Budget Management

Each level imposes thermal constraints on subsequent processing:

• Metal interconnects (Au, Al) limit subsequent processing to < 400°C
• Polymer functional layers may degrade above 150–200°C
• ALD at 150–200°C and low-temperature PECVD (100–300°C) are compatible with most multi-level flows
• Plan the process sequence so high-temperature steps (thermal anneals, oxidation) occur at early levels before temperature-sensitive materials are introduced

7) Equipment Selection for Nanofabrication

The following table maps each nanofabrication process step to the specific NineScrolls equipment designed for that application. Equipment selection depends on the target feature size, material system, and throughput requirements.

8) Troubleshooting Common Nanofabrication Problems

9) Process Integration Example: Plasmonic Nanoantenna Array

To illustrate how the techniques in this guide combine into a complete fabrication flow, here is a step-by-step recipe for a gold bowtie nanoantenna array on a quartz substrate — a common structure for surface-enhanced spectroscopy and biosensing.

1. Substrate preparation: Quartz wafer; piranha clean (H₂SO₄:H₂O₂ 3:1, 10 min, 120°C); O₂ plasma 200 W, 5 min in plasma cleaner
2. Resist coating: Spin MMA EL-11 at 4000 rpm (400 nm); bake 150°C, 5 min. Spin PMMA 950K A4 at 4000 rpm (200 nm); bake 180°C, 5 min. Use coater/developer for reproducible coating
3. E-beam exposure: 100 kV, 300 µC/cm² dose, 10 pA beam current for 50 nm features; apply PEC for bowtie gap uniformity
4. Development: MIBK:IPA 1:3, 90 s; IPA rinse 30 s; blow dry N₂
5. O₂ descum: 50 W, 10 s in compact RIE — removes ~5 nm resist residue from developed areas
6. Metal deposition: E-beam evaporate Cr (2 nm at 0.3 Å/s) / Au (40 nm at 1.0 Å/s) at < 5 × 10⁻⁷ Torr base pressure
7. Liftoff: Soak in warm acetone (55°C, 45 min); gentle sonication; IPA rinse; N₂ dry
8. Final clean: O₂ plasma 50 W, 30 s to remove any organic residue without attacking Au

This flow produces bowtie antennas with gap sizes of 20–30 nm and reproducible plasmonic resonances in the near-IR range. The same general approach — bilayer resist, e-beam patterning, evaporation, liftoff — applies to any noble-metal nanostructure.

Frequently Asked Questions

Glossary

• AR: Aspect Ratio — depth divided by width of a feature
• BCP: Block Copolymer — polymer with two or more chemically distinct blocks that phase-separate at the nanoscale
• CD: Critical Dimension — the smallest feature width that must be controlled in a pattern
• DSA: Directed Self-Assembly — using lithographic templates to guide block copolymer ordering
• EBL: Electron Beam Lithography — direct-write patterning using a focused electron beam
• HSQ: Hydrogen Silsesquioxane — inorganic negative-tone e-beam resist that converts to SiO₂ upon exposure
• IBE: Ion Beam Etching — physical etching using a broad-beam ion source (Ar, Xe)
• L₀: Natural period of a block copolymer’s self-assembled morphology
• LER: Line Edge Roughness — random variation of a feature edge from its intended position
• NIL: Nanoimprint Lithography — pattern transfer by mechanical deformation of a resist
• PEC: Proximity Effect Correction — dose modulation to compensate for electron backscattering
• SAM: Self-Assembled Monolayer — single-molecule-thick film that forms spontaneously on a surface
• χ: Flory-Huggins interaction parameter — quantifies the thermodynamic incompatibility between two polymer blocks; higher χ enables smaller features

Call-to-Action

• Need help selecting the right resist, hardmask, or etch chemistry for your target nanostructure? Our process engineers can evaluate your requirements and recommend a complete fabrication flow.
• Looking for starter recipes for liftoff, nanoimprint, or DSA pattern transfer? We provide process recipe kits tailored to your material system and target feature size.
• Ready for equipment quotation? Contact us for configuration guidance, cleanroom facility checklists, and budgetary pricing.

Contact:
ICP Etcher Series · RIE Etcher Series · ALD Systems · Sputter Systems · Contact us · Email: info@ninescrolls.com

References

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