Photonics Manufacturing: Precision Engineering for Optical Devices

By NineScrolls Engineering · 2024-01-10 · 24 min read · Photonics

Target Readers: Photonics researchers, optical engineers, and process engineers fabricating waveguides, optical coatings, gratings, photonic crystals, or integrated photonic circuits. This guide provides specific etch recipes, deposition parameters, and surface quality requirements for each photonic structure type.

Introduction: Why Photonics Demands Sub-Nanometer Process Control

Photonic devices operate at optical wavelengths (400–1600 nm), where surface roughness, dimensional accuracy, and film uniformity directly translate to optical loss, spectral performance, and device yield. A silicon waveguide with 2 nm RMS sidewall roughness loses ~3 dB/cm at 1550 nm — increasing roughness to 5 nm pushes loss above 10 dB/cm, rendering the device unusable for anything beyond a few hundred micrometers.

This guide focuses on the plasma etching and thin-film deposition processes that determine photonic device performance, with specific recipes and parameters for each major photonic platform.

1) Waveguide Fabrication: The Core of Integrated Photonics

Optical waveguides confine and route light on chip. The waveguide platform determines the available process window, minimum bend radius, and integration density. The three dominant platforms — silicon-on-insulator (SOI), silicon nitride (SiN), and III-V compounds — each impose distinct fabrication requirements.

1.1 Silicon-on-Insulator (SOI) Waveguides

SOI is the dominant platform for telecom-band (1310/1550 nm) photonics due to high index contrast (n_Si ≈ 3.48 vs. n_SiO₂ ≈ 1.44 at 1550 nm) enabling ultra-compact devices with bend radii as small as 5 µm.

Standard strip waveguide etch recipe (220 nm SOI):

Critical process considerations for SOI waveguides:

• Sidewall roughness → propagation loss: The dominant loss mechanism in SOI waveguides is scattering from sidewall roughness. Empirically, propagation loss scales as σ² (roughness variance). Reducing RMS roughness from 3 nm to 1 nm reduces loss by ~9×. The ICP-RIE with independent bias control is essential — it allows maximizing radical density (ICP power) for chemical etching while keeping ion energy (bias) low enough to avoid physical roughening.
• Resist selection: E-beam resist (ZEP-520A or HSQ) produces smoother line-edge roughness than optical photoresist. For production, 193 nm DUV lithography with immersion provides sufficient resolution for 400+ nm wide waveguides.
• Post-etch smoothing: Thermal oxidation (1000°C, 10 min in dry O₂) consumes ~5 nm of Si surface, smoothing roughness by oxidation-driven viscous flow. Subsequent buffered HF dip removes the oxide. This "oxidation smoothing" can reduce roughness from 3 nm to < 1 nm RMS.

1.2 Silicon Nitride (SiN) Waveguides

SiN (n ≈ 2.0 at 1550 nm) offers lower propagation loss than SOI (< 0.1 dB/cm vs. ~1 dB/cm), broader transparency (visible through mid-IR), and better power handling. The lower index contrast requires larger waveguide dimensions (800 nm × 400–800 nm cross-section) and larger bend radii (> 50 µm).

SiN deposition for waveguides:

For research labs developing SiN photonics, a PECVD system with precise gas ratio control (SiH₄/NH₃/N₂) provides the flexibility to tune refractive index and stress independently. Low-temperature PECVD (250–300°C) enables SiN waveguide fabrication on polymer substrates and above existing electronic circuits.

SiN waveguide etch recipe:

• Chemistry: CHF₃/O₂ (10:1) or C₄F₈/SF₆/Ar — fluorocarbon chemistry provides high selectivity to underlying SiO₂ cladding
• ICP/Bias: 500 W ICP / 20–40 W bias; etch rate ~100–150 nm/min
• Pressure: 5–10 mTorr
• Selectivity: SiN:SiO₂ > 5:1; SiN:resist > 3:1
• Sidewall angle: 80–90° achievable; slight taper (85°) acceptable and sometimes preferred for reduced scattering

1.3 III-V Photonic Devices (InP, GaAs)

III-V platforms are essential for active photonic devices — lasers, amplifiers, photodetectors, and modulators. Etching III-V waveguides requires balancing smoothness against chemical selectivity between ternary/quaternary layers.

InP/InGaAsP waveguide etch:

• Chemistry: Cl₂/CH₄/H₂ (ICP-RIE) or HBr/Ar — Cl₂-based provides smooth sidewalls; CH₄/H₂ adds passivation for deep etches
• ICP/Bias: 300–500 W ICP / 50–100 W bias
• Substrate temperature: 200–250°C (critical for InP — low-temp etching produces rough, grass-like surfaces due to InClₓ non-volatility below 150°C)
• Etch rate: 200–500 nm/min; selectivity InP:InGaAsP ~1:1 (minimal selectivity — use etch stop layers)
• Post-etch cleaning: Dilute HCl (1:10) dip removes surface chlorides; (NH₄)₂S passivation reduces surface recombination

2) Optical Coating Deposition

Optical thin-film coatings control reflection, transmission, and absorption at surfaces. Performance depends on precise thickness control, refractive index accuracy, and ultra-low absorption — requirements that map directly to deposition process parameters.

2.1 Anti-Reflection (AR) Coatings

ALD excels for precision AR coatings because each layer's thickness is controlled at the Å-level (< 1% thickness error), ensuring spectral accuracy. For broadband AR stacks with 8+ layers, the cumulative thickness error of PECVD or sputtering (~1–2% per layer) can shift the spectral response enough to require iterative optimization; ALD's self-limiting growth eliminates this issue.

2.2 Distributed Bragg Reflectors (DBRs)

DBRs — alternating λ/4 layers of high-n and low-n dielectrics — provide wavelength-selective mirrors for laser cavities, VCSELs, and optical filters. Performance scales with the number of pairs and the index contrast between layers.

SiO₂/TiO₂ DBR at 1550 nm:

• Layer thicknesses: SiO₂ = 267 nm (n=1.45), TiO₂ = 194 nm (n=2.00)
• 8 pairs provide R > 99%; 12 pairs provide R > 99.9%
• ALD deposition: SiO₂ by BTBAS/H₂O₂ at 200°C (0.8 Å/cycle); TiO₂ by TDMAT/H₂O at 250°C (0.5 Å/cycle)
• Total stack thickness: ~3.7 µm for 8 pairs — manageable by ALD but time-consuming (~12 hours). PECVD reduces this to < 2 hours but with reduced thickness precision.

2.3 Metal-Dielectric Optical Filters

Fabry-Pérot interference filters use metal/dielectric/metal (MDM) structures for narrowband wavelength selection:

• Metals: Ag (lowest absorption), Au (NIR), Al (UV) — deposited by sputtering at 3–5 mTorr Ar, DC 50–100 W, controlled thickness 20–50 nm
• Dielectric spacer: SiO₂ or Al₂O₃ — thickness determines center wavelength. ALD provides the ±0.5 nm accuracy needed for narrowband (< 5 nm FWHM) filters.
• Challenge: Metal film continuity at < 20 nm — island-growth creates absorption losses. Wetting layers (1–2 nm Ge or Cu) or substrate cooling during sputtering improve film coalescence.

3) Diffraction Gratings and Photonic Crystals

Periodic nanostructures — gratings, photonic crystals, and metasurfaces — manipulate light through diffraction and interference. Their performance is exquisitely sensitive to dimensional accuracy and sidewall quality.

3.1 Diffraction Grating Fabrication

3.2 Photonic Crystal Fabrication

2D photonic crystals (arrays of air holes in a high-index slab) require deep, vertical, smooth-walled holes with precise diameter and pitch. This is one of the most demanding etch applications in photonics.

Si photonic crystal etch (triangular lattice, a = 400 nm, r/a = 0.3):

• Hole diameter: ~240 nm, depth 220 nm (through 220 nm Si slab)
• Chemistry: Cl₂/N₂ or HBr/O₂ in ICP-RIE
• ICP/Bias: 600 W ICP / 15 W bias (low bias for minimal roughness inside holes)
• Pressure: 5 mTorr (low pressure for vertical hole profile)
• Etch rate: ~80 nm/min; target etch time ~2:45 for 220 nm
• Critical metric: Hole circularity deviation < 5 nm from perfect circle; measured by top-view SEM. Deviation creates scattering losses that degrade the photonic bandgap quality factor.

InP photonic crystal (for 1550 nm active photonic crystal lasers):

• Deep holes through III-V stack: Aspect ratio 5–10:1; requires Cl₂/CH₄/H₂ at elevated temperature (200°C)
• Challenge: Non-vertical profiles cause gap closure and mode leakage. Add Ar (20%) to improve directionality at the expense of slight roughening.

3.3 Metasurface Fabrication

Metasurfaces — sub-wavelength-thickness patterned layers that control phase, amplitude, and polarization of transmitted/reflected light — are among the hottest areas in photonics research. See our publication spotlight on metasurface color routers fabricated with the RIE-150A and metasurface flow visualization with the ICP-200.

Typical Si metasurface etch (nanopillar array on fused silica):

• Structure: a-Si:H nanopillars, diameter 100–300 nm, height 500–700 nm, pitch 300–500 nm
• PECVD a-Si deposition: SiH₄/H₂ at 250°C, 50 W RF, ~10 nm/min, targeting n ≈ 3.5 at 1550 nm
• Etch: Cl₂/HBr ICP-RIE, 500 W ICP / 15 W bias, 5 mTorr, etch rate ~80 nm/min
• Profile requirement: Near-vertical sidewalls (> 85°) with < 2 nm roughness; pillar diameter tolerance ±5 nm across the array for uniform phase response

4) Integrated Photonic Circuit Process Flows

Complete photonic circuits combine waveguides, couplers, modulators, and detectors on a single chip. Below are representative process flows with specific equipment at each step.

4.1 Silicon Photonic Transceiver (SOI Platform)

1. Starting material: 220 nm Si on 2 µm BOX (buried oxide) on Si handle wafer
2. Waveguide level (full etch): E-beam or DUV lithography → Cl₂/HBr ICP-RIE, 500 W/15 W, 10 mTorr → strip resist (O₂ plasma striper)
3. Rib waveguide level (partial etch, 70 nm slab): Second lithography → Cl₂/HBr ICP-RIE, 300 W/10 W, 15 mTorr, timed etch to leave 70 nm Si slab → strip
4. Grating couplers (shallow etch, 70 nm): Third lithography → same partial etch recipe → strip
5. Doping (p-type/n-type for modulator): Ion implantation through resist windows → activation anneal (1050°C, 10 s RTA)
6. SiO₂ upper cladding: PECVD SiO₂ (SiH₄/N₂O, 300°C), 1–2 µm thick
7. Contact via etch: CHF₃/Ar RIE through SiO₂ to Si contact pads
8. Metallization: Sputter Ti/TiN/Al (10/20/500 nm) → pattern by Cl₂/BCl₃ RIE → liftoff or etch
9. Ge photodetector integration (optional): Selective epitaxial growth of Ge in etched recesses; subsequent doping and contact formation

4.2 SiN Photonic Sensor (Visible/NIR Platform)

1. Substrate: Thermal SiO₂ (3–4 µm) on Si wafer as lower cladding
2. SiN core deposition: PECVD SiN (SiH₄/NH₃, 300°C, target n = 2.0) → thickness 300–400 nm
3. Waveguide patterning: E-beam or stepper lithography → CHF₃/O₂ ICP-RIE → strip resist
4. Upper cladding: PECVD SiO₂, 2–3 µm (provides symmetric cladding for low loss)
5. Sensing window opening: Lithography → CF₄/CHF₃ RIE to expose SiN waveguide in sensing region → strip
6. Surface functionalization: Plasma activation (O₂ plasma, 50 W, 60 s) → silane chemistry for biosensor receptor attachment

5) Surface Quality and Loss Optimization

Optical loss in photonic devices comes from three sources: material absorption, radiation (bending) loss, and scattering loss. Fabrication primarily controls scattering loss, which is determined by surface roughness and dimensional variations.

5.1 Roughness Budget by Platform

5.2 Etch Process Parameters That Control Roughness

• Bias power (ion energy): The single most important parameter. Higher bias increases physical sputtering, creating rougher sidewalls. For photonics, keep bias power at 10–30 W (< 50 eV ion energy). This is the primary reason ICP-RIE outperforms conventional RIE for photonic etch — CCP-RIE cannot independently set low ion energy while maintaining high plasma density.
• Gas chemistry: HBr produces smoother Si sidewalls than Cl₂ (HBr forms a volatile but passivating SiBrₓ layer). Adding O₂ (2–5%) further improves sidewall passivation.
• Pressure: Lower pressure (< 10 mTorr) improves anisotropy but increases physical etch component. 5–15 mTorr is the sweet spot for photonic waveguides.
• Mask quality: Line-edge roughness (LER) of the resist mask transfers directly to waveguide sidewall roughness. Use high-contrast resists (HSQ, ZEP-520A) and optimized e-beam dose to minimize mask LER.
• Chamber condition: Polymer buildup on chamber walls creates particle contamination that acts as micro-masks. Regular chamber cleaning and conditioning wafers between process runs are essential.

6) Thin Film Quality for Photonic Applications

Photonic thin films must meet stricter optical requirements than electronic films — absorption coefficient, refractive index accuracy, and thickness uniformity all directly impact device performance.

6.1 Film Quality Comparison by Deposition Method

For photonic applications, ALD provides the best optical quality but lowest throughput. PECVD is the practical choice for thick cladding layers (2–4 µm) where absorption can be managed by post-deposition annealing (reducing Si-H and N-H bonds). A common hybrid approach: PECVD for thick cladding + ALD for precision coatings on the waveguide surface.

7) Equipment Selection for Photonics Labs

Conclusion

Photonic device performance is fundamentally limited by fabrication quality — sidewall roughness, dimensional accuracy, and film optical properties. Unlike electronic devices where a 5% variation in feature size may cause modest parameter shifts, a 5% variation in waveguide width or grating pitch can shift operating wavelength by tens of nanometers, rendering the device non-functional for its intended application.

The recipes and parameters in this guide represent proven starting points for the major photonic platforms. The critical take-away for equipment selection: ICP-RIE with independent, low-bias capability is non-negotiable for waveguide fabrication, and deposition systems must provide the refractive index accuracy (±0.01 for PECVD, ±0.002 for ALD) that optical applications demand.

References and Further Reading

• Bogaerts, W., et al. "Silicon microring resonators." Laser & Photonics Reviews 6(1), 47–73 (2012).
• Baets, R., et al. "Silicon photonics: silicon nitride versus silicon-on-insulator." Optical Fiber Communication Conference, Th3J.1 (2016).
• Hochberg, M. & Baehr-Jones, T. "Towards fabless silicon photonics." Nature Photonics 4, 492–494 (2010).
• Saleh, B. E. A. & Teich, M. C. Fundamentals of Photonics, 3rd ed. Wiley (2019).
• Chrostowski, L. & Hochberg, M. Silicon Photonics Design. Cambridge University Press (2015).
• NineScrolls. "The Complete Guide to Reactive Ion Etching"
• NineScrolls. "RIE-150A Metasurface Color Router"
• NineScrolls. "ICP-200 Metasurface Flow Visualization"