TSMC Unveils A13 1.3nm Node, Arizona Packaging Plant by 2029, and Pauses ASML High-NA EUV Adoption

By NineScrolls Team · 2026-04-25 · 5 min read · Industry

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TSMC Debuts A13 at the 2026 North America Technology Symposium

At the 2026 North America Technology Symposium in Santa Clara, TSMC unveiled A13, branded as a 1.3nm-class node and positioned as the direct successor to its already-announced A14. A13 is scheduled to enter production in 2029, one year after A14 ramps in 2028.

According to TSMC, A13 delivers a roughly 6% area reduction over A14 by shrinking linear dimensions by about 3%, while preserving full design-rule and electrical compatibility with A14. The company is positioning A13 as a low-friction migration path that delivers added power and performance gains through design-technology co-optimization (DTCO) rather than through a wholesale process reset.

The reveal extends TSMC's nodename cadence into the angstrom era and gives customers a visible 2027–2029 path: A16 (1.6nm) volume production in 2027, A14 GAA in 2028, then A13 and A12 in 2029.

N2U Extends 2nm to 2028, A12 Joins A13 in 2029

Alongside A13, TSMC introduced N2U, a third-year extension of its N2 (2nm) platform targeted for 2028. N2U leverages DTCO to deliver about 3%–4% higher performance at the same power, or 8%–10% lower power at the same speed, with a 2%–3% logic-density improvement, while remaining IP-compatible with N2P.

TSMC framed N2U as a balanced option for AI, HPC, and mobile customers that want incremental gains without absorbing the cost of moving to a fully new platform. A12 (1.2nm), also slated for 2029, fills out the dual-track 2029 lineup.

A16, TSMC's 1.6nm node featuring Super Power Rail backside power delivery, has slipped from late 2026 to volume production in 2027, according to TrendForce reporting on the symposium.

Arizona Advanced Packaging Plant Targets 2029 for CoWoS and 3D-IC

TSMC also confirmed plans to bring advanced packaging to its Arizona campus before 2029. The company will install both CoWoS (Chip-on-Wafer-on-Substrate) and 3D-IC capacity in Arizona, the same platforms used today for Nvidia's AI accelerators and Apple's high-end silicon.

The move closes a gap in TSMC's U.S. supply chain. Today, wafers fabricated at TSMC Arizona's Phoenix fabs still travel back to Taiwan for advanced packaging and testing — a logistics step that adds weeks and cost to AI accelerator production. Construction on the Arizona packaging site has already begun, according to company executives.

Amkor, TSMC's longtime packaging partner, is racing the same finish line: its own Arizona advanced-packaging facility is targeting early 2028, giving it roughly a one-year head start over TSMC's in-house line.

TSMC Holds Off on ASML High-NA EUV Through 2029

The most consequential disclosure for the equipment supply chain came on cost. TSMC Deputy Co-Chief Operating Officer Kevin Zhang told reporters at the symposium that A14, A13, and A12 will all be built without ASML's High-NA EUV tools, calling the next-generation lithography platform "very, very expensive" and indicating TSMC will continue using current EUV through at least 2029.

ASML's TWINSCAN EXE:5000-series High-NA scanners list at upwards of €350 million ($410 million) per unit, roughly double the price of standard EUV. ASML shares fell about 3% on April 22 after the announcement, as analysts trimmed their forecasts for High-NA shipments through the decade.

To compensate, TSMC is leaning harder on multi-patterning, DTCO, and packaging-driven density. The 6% area gain on A13 versus A14 — modest by historical full-node standards — signals that lithography alone is no longer the primary density lever; advanced packaging, atomic-layer process control, and design optimization are picking up the load.

What This Means for Plasma Processing and Thin Film Deposition

TSMC's decision to extend current EUV through three more nodes shifts work onto the etch and deposition tool base. Producing A14, A13, and A12 features without High-NA means more LELE/LELELE multi-patterning passes, which multiply the number of plasma etch and PECVD/ALD spacer-formation steps per critical layer. Each additional litho-etch cycle is an additional plasma process — exactly the workload that has driven Lam Research and Tokyo Electron etch backlogs through 2026.

Backside power delivery on A14, and continued density work on A13/A12, push wafer-edge process complexity into deeper trench etching, high-aspect-ratio via fill, and conformal ALD of barrier and liner films. Molybdenum, ruthenium, and tungsten thin-film deposition — by ALD and CVD — gain volume as multi-patterning replaces resolution. Dielectric PECVD for low-k spacers and high-k gate stacks at GAA nodes scales with the same logic.

The Arizona packaging build-out is the parallel story for the equipment supply chain. CoWoS and 3D-IC lines run on PVD/sputter for redistribution-layer (RDL) metallization, plasma surface activation for hybrid bonding, dielectric CVD/PECVD for interposer passivation, and deep silicon plasma etch for through-silicon vias (TSVs). Bringing those processes onshore by 2029 means net-new tool orders for sputter cathodes, plasma activation chambers, vacuum components, gas delivery, and process monitoring on U.S. soil — adding to the demand pull from the four Phoenix fabs already in build-out.

The High-NA pause is not a lost dollar; it is a redistributed one. The capex that would have funded €350 million scanners flows instead to the equipment that compensates: more etch chambers per fab, more deposition reactors per layer, and a larger packaging install base in Arizona. For NineScrolls and the broader plasma processing and thin film deposition supply chain, that is the trend line to track.

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