TSMC Ramps 2nm Production Toward 140,000 Wafers per Month, Driving Record Deposition Equipment Demand
By NineScrolls Team · 2026-03-15 · 2 min read · Industry
Table of Contents
- The 2nm Ramp
- Capacity Targets
- Process Performance
- Samsung and Intel in Pursuit
- Equipment Demand Implications
The 2nm Ramp
TSMC commenced volume production of its 2nm (N2) process on December 31, 2025, marking the world's first commercial deployment of gate-all-around (GAA) nanosheet transistors at this node. Initial output began at Fab 22 in Kaohsiung, Taiwan, with Fab 20 expected to follow.
All 2nm capacity for 2026 is already fully booked. Apple accounts for more than half of initial orders, with other major customers including Qualcomm, MediaTek, and Nvidia vying for remaining allocation.
Capacity Targets
TSMC plans to reach 140,000 wafers per month by end of 2026, exceeding earlier projections of 100,000 to 130,000. The company targets 200,000 wafers per month by 2027. This aggressive ramp requires massive investment in advanced deposition, etch, and lithography equipment across multiple fabs.
An enhanced variant, N2P, featuring further performance and power improvements, is scheduled for volume production in the second half of 2026, adding another wave of equipment procurement.
Process Performance
TSMC's N2 delivers a 10 to 15 percent performance gain at equivalent power, a 25 to 30 percent reduction in power at equivalent performance, and a 15 percent increase in transistor density compared to the N3E node. Initial yield rates have reached approximately 70 percent, which TSMC considers strong for an early ramp of this complexity.
Samsung and Intel in Pursuit
Samsung is targeting 21,000 wafers per month of its own 2nm GAA process by end of 2026. Intel scrapped its original 2nm plan in favor of the 18A (1.8nm) node, which uses its own GAA implementation called RibbonFET. Both face yield gaps relative to TSMC, leaving TSMC as the sole high-volume external supplier at this node for the foreseeable future.
Equipment Demand Implications
GAA architectures require significantly more process steps than FinFET. Industry data shows that ALD steps per wafer have increased over 20 percent at the 2nm node. Each additional deposition and etch step translates directly into demand for plasma processing chambers, ALD tools, vacuum systems, and associated consumables.
With TSMC alone targeting 140,000 wafers per month at 2nm, and Samsung adding another 21,000, the combined equipment pull from just this node represents one of the largest single-generation demand drivers in semiconductor manufacturing history.