SanDisk and SK Hynix Activate HBF Equipment Supply Chain — TSV Etch, ALD, and PECVD Tools in Demand for Stacked NAND

By NineScrolls Team · 2026-04-14 · 6 min read · Industry

What Is HBF and Why Does It Matter for AI?

High Bandwidth Flash (HBF) is an emerging memory architecture that stacks multiple 3D NAND dies vertically and connects them to a logic base die through through-silicon vias (TSVs) — the same interconnect approach used in HBM (High Bandwidth Memory). The key difference: HBF uses NAND flash instead of DRAM, trading raw speed for dramatically higher capacity at lower cost per bit.

A standard HBF stack targets approximately 1.6 TiB of capacity — roughly sixteen times more than an HBM4 stack (~100 GiB) — with aggregate bandwidth of 400–800 GB/s per stack. Per-stack power is estimated at 20–80 W, yielding bandwidth-per-watt greater than 6.4 GB/s/W. The architecture is positioned for AI inference servers, where high-capacity, lower-latency storage close to the GPU is more valuable than the raw bandwidth HBM provides.

On February 25, 2026, SanDisk and SK Hynix formally announced they had begun global standardization of HBF, the first step toward establishing a shared interface specification that GPU vendors and system OEMs can design against. Samsung Electronics and Kioxia are separately developing their own HBF products, and Chinese startup FlashDi has announced plans for an HBF pilot production line in H2 2026 targeting mass production in 2027.

TSV Architecture Drives Complex Etch and Deposition Requirements

HBF's manufacturing complexity comes from combining two distinct process families in a single package: 3D NAND fabrication and TSV-based advanced packaging. Each layer of the NAND stack requires hundreds of CVD and ALD deposition cycles for wordlines, tunneling oxides, and inter-layer dielectrics. The TSV interconnects then punch through the entire stack, requiring deep silicon etch followed by dielectric liner deposition, barrier deposition, and metal fill.

The specific process steps that drive HBF tool demand are:

TSV deep silicon etch — ICP etch of high-aspect-ratio vias (typically 10:1 to 20:1) through hundreds of microns of silicon, using the Bosch process (alternating SF₆ etch and C₄F₈ passivation cycles) to maintain vertical sidewalls without undercutting.
TSV dielectric liner — PECVD SiO₂ conformal deposition at low temperatures (<400 °C) to electrically isolate the via from the bulk silicon. Thickness uniformity inside deep vias is critical; non-uniformity above ±2% risks leakage or inter-die shorts after bonding.
Barrier/adhesion layer — ALD TaN or TiN at 3–10 nm, deposited conformally inside the TSV prior to copper seed. ALD is the only deposition method with the step coverage required for these via geometries.
PVD copper seed — Magnetron sputtering of a thin (~50–100 nm) copper seed layer on top of the ALD barrier, enabling subsequent electrochemical copper fill.
Oxide and nitride deposition for the NAND stack — ALD and CVD alternating SiO₂/Si₃N₄ or SiO₂/poly-Si for wordline stack formation. A 200-layer NAND die may require more than 400 individual deposition steps.

The result is a tool mix that looks like a hybrid of a 3D NAND fab and an advanced packaging line — with plasma etch and thin film deposition tools doing the heaviest lifting at both ends of the process flow.

SanDisk Activates Equipment Supply Chain — April 2026

Industry sources reported in the week of April 13, 2026 that SanDisk has moved beyond early concept work and begun actively engaging equipment and materials partners for an HBF prototype production line. Some companies are already in purchase-order negotiations. The timeline targets major equipment installation in H2 2026, with prototype samples available by year-end and commercial production in 2027.

The supply chain buildout follows the SanDisk–SK Hynix standardization announcement of February 25 and signals that both companies are treating HBF as production-bound, not just a research project. SK Hynix has been working on HBF since at least late 2025, and the two companies' collaboration on a common interface spec is intended to attract GPU vendors — particularly Nvidia — that need a single addressable standard before committing HBF to server platform designs.

The NAND undersupply that SanDisk flagged in late 2025 — projected to extend beyond 2026 into 2027 — adds urgency to the HBF buildout. Capacity expansions that go toward HBF production effectively remove wafer starts from the commodity NAND supply pool, which tightens the market further and supports pricing. Equipment orders placed now for pilot-line tools will flow into broader production ramp tools in 2027 if yield results from the H2 pilot are satisfactory.

Samsung and Kioxia Enter the HBF Race

Samsung Electronics is independently developing HBF and has reportedly begun preliminary engagement with packaging and equipment partners. In March 2026, Kioxia (formerly Toshiba Memory) announced it was targeting GPU memory stacks with a high-bandwidth flash push, positioning HBF as a complement — not a replacement — for HBM in AI server memory hierarchies. With three memory majors (SanDisk/SK Hynix partnership, Samsung, Kioxia) and at least one Chinese entrant (FlashDi) all pursuing HBF production by 2027, the equipment demand window is converging in H2 2026 through 2028.

The competitive parallel to HBM's emergence in 2015–2018 is direct: once GPU vendors commit to a standard interface for HBF, system architects will design memory hierarchies that require a given number of HBF stacks per server node, and fab capacity becomes the gating resource. Tool vendors that qualify for HBF pilot lines in 2026 will be positioned first for the production ramp tools in 2027–2028.

NineScrolls Niche Angle: What HBF Means for Plasma and Thin Film Equipment

Plasma processing equipment (ICP etch, RIE, plasma activation). TSV deep silicon etch is the defining ICP etch application in advanced packaging. Bosch-process ICP etchers operating at high source power (1,000–3,000 W at 13.56 MHz or 2 MHz) and low bias (~50–200 V) are required to achieve the scallop depths and etch uniformity tolerances that TSV profiles demand. As HBF scales from prototype to production, ICP etch tool count per fab tracks directly with TSV via density and wafer throughput. PECVD tools are equally critical for the conformal SiO₂ liner step — low-temperature PECVD with good step coverage at high aspect ratios is a standard capability of research and pilot-line PECVD systems.

Thin film deposition systems (ALD, CVD, PVD/sputtering). ALD is non-negotiable for TSV barrier deposition. The 10:1–20:1 aspect ratios required for TSV interconnects in stacked-die packages cannot be covered by PVD; only ALD delivers the sub-10 nm TaN/TiN conformality required. Magnetron sputtering (PVD) then deposits the copper seed layer on the ALD barrier — the two processes are sequential and typically performed in integrated cluster tools. For the NAND stack itself, ALD/CVD equipment running the alternating oxide/nitride or oxide/poly stack cycles constitutes the largest deposition tool count in the entire flow. A 200-layer 3D NAND die with a 150-nm pitch requires sub-2 nm thickness control per layer.

Equipment supply chain implications. HBF adds a new equipment demand vector on top of the existing HBM capacity expansion already consuming ICP etch, ALD, and PECVD tools across SK Hynix, Samsung, and Micron fabs. Research and pilot-line facilities — the natural entry point for HBF in 2026 — are precisely the market segment that requires the versatile, configurable plasma etch and deposition platforms that NineScrolls specializes in. University nanotech centers and advanced packaging research labs developing HBF-compatible process flows will need capable ICP etch, PECVD, ALD, and sputtering tools with the flexibility to run and optimize novel TSV and dielectric recipes.