Samsung Ships Industry-First 12-Layer HBM4E Samples at 3.6 TB/s, Six Months Ahead of SK Hynix

By NineScrolls Team · 2026-05-31 · 5 min read · Industry

Samsung Begins HBM4E Sample Shipments — May 29, 2026

Samsung Electronics on May 29, 2026 began shipping the industry's first 12-layer HBM4E samples to major global customers, extending its high-bandwidth memory roadmap only three months after HBM4 entered mass production in February 2026.

The announcement places Samsung at least several months ahead of SK Hynix, whose own HBM4E sample shipments had been guided for the second half of 2026, with mass production targeted for 2027. Neither SK Hynix nor Micron had publicly confirmed HBM4E sample deliveries as of May 30, 2026.

The Numbers: 16 Gbps, 3.6 TB/s, 48 GB Per Stack

Samsung's HBM4E samples run at a stable 14 Gbps per pin that scales to 16 Gbps under load — a more than 20% improvement over HBM4's 11.7 Gbps qualified speed — and deliver 3.6 TB/s of per-stack bandwidth. Capacity rises to 48 GB per 12-layer stack, more than 30% above HBM4's 36 GB configuration.

Power and thermal performance also stepped up: Samsung cites a 16% improvement in energy efficiency and a more than 14% improvement in thermal resistance versus HBM4, both driven by advanced low-power design techniques and optimized packaging structures.

Samsung plans to extend the lineup to 32 GB 8-layer and 64 GB 16-layer configurations as customer requirements crystallize. Mass production timing remains "aligned with customer schedules, following initial sample shipments and optimization."

1c DRAM and 4nm Logic Base — Process Continuity From HBM4

HBM4E reuses the same two manufacturing building blocks Samsung qualified for HBM4: its sixth-generation 10-nanometer-class DRAM process — designated "1c" — for the memory die, and Samsung Foundry's 4nm logic base die. Industry observers cited by TrendForce note that the shared core and base die combination should make the transition to HBM4E mass production smoother than typical generation-to-generation jumps that require entirely new process qualification.

Sang Joon Hwang, Executive Vice President and Head of Memory Development at Samsung Electronics, said: "Following the successful mass production of HBM4, Samsung has once again demonstrated its distinct technological edge with HBM4E."

Where SK Hynix and Micron Stand in the HBM4E Race

SK Hynix held 57% of global HBM revenue in Q3 2025 per Counterpoint Research, with Samsung at 22% and Micron at 21%. SK Hynix also secured roughly two-thirds of Nvidia's 2026 HBM4 allocation for the Vera Rubin platform, reflecting years as Nvidia's primary HBM supplier.

The HBM4E sampling lead resets that timeline. The qualification window — where Nvidia, AMD and hyperscalers validate signal integrity, thermal behavior and accelerator compatibility — takes months and effectively dictates downstream design wins. Micron's entire 2026 HBM4 capacity is already committed, leaving it watching the HBM4E qualification race from a position similar to SK Hynix.

A $76 Billion HBM Market in 2026, $156 Billion by 2027

BNP Paribas analysts project the global HBM market will more than double to roughly $76 billion in 2026, rising to an estimated $156 billion in 2027. Samsung describes itself as the only semiconductor company capable of supplying HBM from memory through logic, foundry and advanced packaging under one roof — a turnkey positioning aimed at locking in AI-accelerator customers whose infrastructure timelines are already set.

Samsung has completed 1c DRAM equipment installation in its P2 Pyeongtaek fab and is simultaneously bringing in new equipment at P3 and P4 to support HBM4 and HBM4E ramps, with back-end packaging stabilization assistance from Hanmi Semiconductor.

What This Means for Plasma Processing and Thin Film Deposition

Plasma processing equipment. A 12-layer HBM4E stack at 48 GB depends on through-silicon vias (TSVs) etched with high-aspect-ratio plasma etchers and on hybrid bonding interfaces prepared by plasma activation. Each additional layer above the 8-Hi baseline multiplies the number of TSV etch passes, dielectric PECVD steps and plasma-clean cycles per wafer. The 1c DRAM node itself relies on advanced reactive ion etch and atomic layer etch tools to define sub-15nm gate and bitline features without damaging the underlying dielectric stack.

Thin film deposition systems. 1c DRAM and the 4nm foundry base die both push ALD and PECVD intensity higher. High-k gate dielectrics, low-k interlayer dielectrics and barrier metals for the base die's interconnect stack are deposited layer-by-layer with ALD and CVD reactors. PVD and sputtering tools deposit the copper seed, barrier metals and bond pads required for hybrid bonding between the logic base and the DRAM stack. A 16-layer HBM4E variant — already on Samsung's roadmap — would lift deposition step counts by roughly another third per stack.

Equipment supply chain. The same Pyeongtaek tool buildout that produces HBM4 and HBM4E pulls on plasma sources, ESC components, RF generators, vacuum pumps and chambers; on PVD targets in copper, titanium and tantalum; on ALD precursor delivery and gas panels; and on residual gas analyzers and OES sensors for chamber matching. Samsung's signal that mass-production timing depends on accelerator-vendor qualification, not on its own readiness, means equipment utilization at the new 1c lines should run hot through 2026 and into 2027 as customers complete qualification and order volumes shift from HBM4 to HBM4E.