Samsung Pulls Forward P5 Fab 2 by Six Months, Commits $82.7 Billion to a 600,000-Wafer Pyeongtaek Megasite

By NineScrolls Team · 2026-05-13 · 6 min read · Industry

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P5 Fab 2 Groundbreaking Pulled to July 2026

Samsung Electronics will break ground on P5 Fab 2 — the final production line at its Pyeongtaek campus in South Korea — in July 2026, approximately six months ahead of the originally planned early-2027 start. P5 Fab 2 will run in parallel with P5 Fab 1, which resumed construction in late 2025 after an 18-month halt triggered by Samsung's 2023 semiconductor losses.

The decision marks a decisive pivot from cost discipline to speed. After Samsung's semiconductor division posted a ₩15 trillion (~$10.3 billion) loss in 2023 and froze the P5 Fab 1 site eight months after groundbreaking, the AI-driven memory shortage has flipped the calculus. Samsung's semiconductor division returned to a ₩57 trillion (~$39.3 billion) operating profit in Q1 2026.

₩120 Trillion ($82.7 Billion) Across P5 Fab 1 and Fab 2

Samsung has committed approximately ₩120 trillion (~$82.7 billion) to the combined P5 Fab 1 and Fab 2 buildout, with the two lines projected to deliver 600,000 wafers per month of 300mm capacity when fully operational in 2029. That single megasite output rivals Samsung's current total DRAM production of roughly 650,000 wafers per month.

The P5 investment sits inside Samsung's broader ₩110+ trillion (~$73 billion) 2026 capex envelope — the largest single-year semiconductor capital outlay by any company on record. Industry analysts estimate roughly $40 billion of the 2026 budget flows directly to wafer-fab equipment.

A Multi-Fab Mix: HBM4, 1c/1d DRAM, 400-Layer V-NAND, Foundry

P5 Fab 2 will be built as a "multi-fab" engineered to flex between product lines based on demand. The campus will house HBM lines, sixth-generation 10nm-class (1c) and seventh-generation (1d) DRAM, 400-layer-class V-NAND, and advanced-node foundry capacity in a single integrated site.

The NAND component is particularly significant. Samsung is moving its 9th-generation (286-layer) V-NAND into production at Pyeongtaek P1 and has staged 10th-generation V-NAND — over 400 layers with hybrid bonding between the cell wafer and peripheral CMOS wafer — for ramp inside the same 2027–2029 window. The 400-layer node uses bonded-vertical-NAND (BV-NAND) architecture to lift bit density approximately 1.6× over the prior generation.

DDR4 spot pricing illustrates the demand pressure driving the acceleration. Fixed transaction prices for legacy PC DDR4 climbed from $1.65 in April 2025 to $16 in April 2026 — nearly a 10× rise in one year, according to DRAMeXchange.

SK Hynix and Micron Push the Three-Way Race

SK Hynix is installing DRAM production equipment for a 70,000 wafers/month line at its M15X fab in Cheongju within 2026, and has pulled forward cleanroom operation at its first Yongin Cluster fab from May 2027 to February 2027 — a three-month acceleration. Yongin will anchor SK Hynix's 1c DRAM volume and, by extension, the company's seventh-generation HBM4E roadmap. CFO Kim Woo-hyun told investors on the Q1 2026 earnings call that capex will see a "substantial increase" year-over-year.

Micron is moving in parallel. The company is building advanced HBM-capable memory fabs in New York (a $100 billion multi-decade megafab project) and Idaho, and is expanding its Hiroshima site. Combined capacity from the three programs is expected to come online within two to three years.

Tokyo Electron, Advantest, Disco Lead Nikkei 3,300-Point Surge

Equity markets registered the equipment-spending implications immediately. On May 7, the Nikkei 225 closed at 62,833.84, up 3,320.72 points in a single session, with semiconductor manufacturing equipment names leading the rally. Tokyo Electron (8035.T), Advantest (6857.T), Disco (6146.T), Shin-Etsu Chemical (4063.T), and Ibiden (4062.T) all posted notable gains. Trading value on the TSE Prime Market hit ¥10.84 trillion (~$5.4 billion), with 75.6% of issues advancing.

The Philadelphia Semiconductor Index (SOX) had risen a cumulative 9.23% over the prior four trading days, partly on strong AMD results, reinforcing buying in chip-equipment and electronic-component names in Tokyo.

What This Means for Plasma Processing and Thin Film Deposition

A 600,000 wafers/month megasite mixing HBM, 1c/1d DRAM, 400-layer V-NAND, and advanced foundry is, in equipment terms, one of the most plasma- and deposition-intensive workloads ever planned at a single site. The order book impact is broad and deep.

Plasma etch — the chokepoint for 400-layer V-NAND. Memory channel-hole etch through 400+ alternating oxide/nitride layers requires aspect ratios above 60:1 and depths approaching 10 µm. This is the most demanding production plasma-etch step in semiconductor manufacturing. Tokyo Electron's cryogenic hydrogen-fluoride channel-hole etch (announced for 400-layer-class 3D NAND) delivers up to 5× faster etch rates with substantially lower global-warming-potential gases, and Lam Research's DirectDrive pulsed-power architecture (50-µs switching) is positioned to define the same process window. Every P5 NAND wafer will also need conductor and dielectric etch sets for the staircase, slit, and word-line cuts — consuming dozens of etch chambers per 1,000 wafers/day.

Thin film deposition — ALD, PECVD, and PVD all scale at once. 400-layer V-NAND begins with hundreds of PECVD oxide/nitride pairs deposited on a single wafer before any etch occurs — the ONON or OPOP stack is the workhorse of memory-fab CVD throughput. Amorphous-carbon hard-mask (ACL) deposition is needed to survive the channel-hole etch, and ALD high-k dielectric and metal-gate films coat the channel and word-line stacks at sub-angstrom precision. On the HBM side, every 1c DRAM capacitor requires ALD high-k dielectric, and HBM4 stacks demand PVD barrier and seed layers for through-silicon vias plus plasma-activated hybrid-bonding interfaces between dies. Applied Materials, Tokyo Electron, Lam Research, and ASM International are the primary tool suppliers.

Equipment supply chain — lead times stretch across the board. A 600,000 wafers/month buildout running 2027–2029 lands on top of TSMC's Arizona and 2nm ramps, SK Hynix's M15X and Yongin install, and Micron's New York/Idaho/Hiroshima programs. RF plasma sources (Advanced Energy, MKS, Comet), turbomolecular and dry vacuum pumps (Edwards, Pfeiffer, Ebara), high-purity sputtering targets (JX Advanced Metals, Materion, Honeywell), mass flow controllers and gas-delivery systems (Brooks, Horiba, MKS), and process-monitoring tools (Onto Innovation, Camtek, KLA) are all running against sustained, multi-year demand. The current capex cycle is shifting from "boom" framing into structural baseline — equipment makers across the supply chain are being asked to commit to multi-year capacity additions of their own.

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