Samsung Pitches MediaTek a Memory-for-Foundry Bundle to Pry 2nm Dimensity Volume From TSMC

By NineScrolls Team · 2026-05-26 · 6 min read · Industry

The Pitch in Hsinchu

Samsung Electronics Chairman Lee Jae-yong landed in Taiwan on May 21, 2026 and went directly to MediaTek's headquarters at the Hsinchu Science Park for closed-door talks. According to DigiTimes and multiple South Korean and Taiwanese outlets, his delegation met MediaTek Chairman Ming-Kai Tsai and Chief Executive Rick Tsai, among other senior executives. The stated objective: secure foundry orders from MediaTek and chip away at Taiwan Semiconductor Manufacturing Company's grip on the world's second-largest mobile-SoC designer.

Neither Samsung nor MediaTek has confirmed the agenda or any terms on the record, leaving the discussion unverified. But the visit marks Samsung's most aggressive executive-level push yet to redirect MediaTek's manufacturing away from TSMC, and it follows a documented pattern of chairman-level outreach by Samsung's leadership.

What Samsung Is Offering

The core of the pitch is a "package deal": priority access to Samsung's high-bandwidth memory (HBM) and DRAM at preferential terms, bundled with an offer to manufacture MediaTek's Dimensity application processors on Samsung's 2-nanometer foundry process. HBM is the stacked memory that sits beside AI accelerators; DRAM is the working memory surrounding mobile and server processors. Both are areas where Samsung holds scale advantages no pure-play foundry can match.

The logic is straightforward. A foundry without an in-house memory business cannot extend guaranteed memory allocation as a sweetener. Samsung can — and with its HBM4 output already heavily committed to AI customers including OpenAI, preferential Dimensity allocation becomes a concrete carrot at a moment when on-device AI workloads are inflating DRAM footprints across the industry.

Strike Resolution and a DRAM Squeeze

The timing was not coincidental. Lee boarded the flight to Taipei less than 24 hours after Samsung's largest union — representing more than 45,000 workers — suspended an 18-day strike that threatened to remove up to 4 percent of global DRAM supply. A government-mediated agreement on performance bonuses, reached late on May 20, averted a walkout that Seoul had warned could harm the broader economy. Samsung shares climbed more than 6 percent the following day.

Without that resolution, a pitch built on guaranteed HBM and DRAM allocation would have rung hollow. The macro backdrop sharpens the leverage further: AI infrastructure investment drove a near-doubling of DRAM contract prices in the first quarter of 2026, turning Samsung's position as the world's largest memory chipmaker into a bargaining instrument it is now using to pry foundry orders loose from TSMC.

The Tesla–Qualcomm Playbook and Samsung's 2nm Turnaround

The bundle structure mirrors the strategy Samsung used in 2024 and 2025 to win foundry orders from Tesla and Qualcomm. The clearest precedent is a confirmed $16.5 billion multi-year contract, signed in July 2025, to build Tesla's next-generation AI6 chip at Samsung's $37 billion fab in Taylor, Texas, which is scheduled to begin operations in the second half of 2026. Qualcomm has also routed certain Snapdragon variants to Samsung-built nodes.

Samsung Foundry's candidacy is more credible than it was a year ago. Reported 2-nanometer yields, which stood near 20 percent in late 2025, had climbed to an estimated 55 to 60 percent by early 2026 according to industry sources — still below TSMC, but a sharp recovery from the lows that drove customer defections in 2024. Samsung is using its 2nm mass-production debut, the Exynos 2600 in the Galaxy S26, as a proof-of-process for external customers. Counterpoint Research's Kyeong-su Kang has assessed that Samsung is positioned to grow foundry volume in 2026 as average selling prices improve and 2nm capacity comes online.

The Skeptics: Cost, Yield, and the Case Against a Full Switch

Analysts uniformly describe an outright displacement of TSMC as difficult. TSMC manufactures the overwhelming majority of MediaTek's volume and retains unmatched depth in advanced packaging — CoWoS in particular. Counterpoint's Jake Rhy has noted that the decisive question about TSMC is no longer raw wafer capacity but system-level integration, making packaging capability as important as process-node leadership. Supply-chain sources cited in trade coverage argue the timing alone makes a wholesale shift of 2nm orders impractical in the near term.

Cost cuts both ways. Counterpoint estimates 2nm wafer costs run roughly 30 percent above 3nm, squeezing fabless margins at Qualcomm and MediaTek alike — which gives both Samsung and MediaTek a reason to negotiate a second source. MediaTek is already diversifying: it is pairing TSMC's CoWoS for training-class AI chips with Intel's EMIB packaging for inference variants whose physical size exceeds CoWoS limits, and it brought on former TSMC advanced-packaging executive Douglas Yu as an advisor in 2026. What Samsung realistically targets is a partial shift — enough volume to validate its 2nm process against a marquee customer and lift utilization at Taylor. The verifiable signal will be the foundry MediaTek names for its next Dimensity flagship; its current 2nm-class Dimensity 9600 launched on TSMC's N2P in the Xiaomi 18 this past January.

What This Means for Plasma Processing and Thin Film Deposition

A MediaTek foundry decision is, beneath the headline, a question of where leading-edge etch and deposition demand physically lands. A 2nm gate-all-around (GAA) nanosheet flow is among the most deposition- and plasma-intensive processes in the industry: atomic layer deposition (ALD) builds the high-k gate dielectric and work-function metal stacks; atomic layer etch and highly selective plasma etch perform the nanosheet channel release and inner-spacer formation; PECVD lays down spacers, liners, and low-k dielectrics; and PVD sputters the barrier and seed layers for interconnect. Whether those steps run in Samsung's Taylor and Pyeongtaek lines or in TSMC's N2 fabs, the tool intensity per wafer is comparable — what shifts is the equipment install base, qualification work, and supplier mix tied to the winning fab.

For the equipment supply chain, the more immediate read is utilization. Samsung's stated need is to run new 2nm capacity — most visibly the $37 billion Taylor, Texas fab — closer to full. A confirmed marquee logic customer accelerates tool installs, chamber qualification, and the recurring pull-through of plasma sources and RF/microwave power delivery, turbomolecular pumps, mass-flow controllers and throttle valves, sputter targets and ALD precursors, and in-situ process monitoring and metrology. The memory half of the bundle reinforces the same theme from the other direction: HBM4 and advanced DRAM are themselves etch- and deposition-heavy, leaning on high-aspect-ratio capacitor etch, high-k ALD, and through-silicon-via (TSV) deep reactive-ion etch for stack integration.

The packaging angle closes the loop. MediaTek's dual CoWoS-plus-EMIB strategy pulls advanced-packaging deposition and etch — TSV DRIE, redistribution-layer PVD seed and plating, dielectric PECVD, and the plasma surface activation that precedes hybrid bonding — regardless of which front-end foundry it chooses. For NineScrolls, the takeaway is that a foundry reshuffle at the customer level does not shrink the addressable market for plasma and thin-film tooling; it redistributes it, and the suppliers of plasma sources, vacuum components, gas delivery, targets, and process monitoring are insulated on either side of the TSMC-versus-Samsung outcome.