NEO Semiconductor Validates 3D X-DRAM in Silicon, Backed by Acer Founder Stan Shih — Built Entirely on 3D NAND Equipment

By NineScrolls Team · 2026-05-15 · 4 min read · Industry

What Happened

NEO Semiconductor announced successful proof-of-concept (POC) silicon results for its 3D X-DRAM technology, a vertically stacked DRAM architecture aimed at AI and data-centric systems. The milestone moved the design from theory to a fabricated, electrically tested device. Trade coverage of the result, including a detailed press release carried by StorageNewsletter, ran on May 13, 2026.

Alongside the POC, NEO disclosed a new strategic investment led by Stan Shih — founder and former chairman and CEO of Acer, and a TSMC board director for more than 20 years — together with a group of technology investors. The funding paid for the POC work and will carry the company into array-level implementation and multi-layer test chips.

The Proof-of-Concept Numbers

The POC test chips were fabricated and put through extensive electrical and reliability evaluation. NEO reported read/write latency under 10 nanoseconds, data retention greater than 1 second at 85°C — roughly 15× better than the 64 ms JEDEC retention standard — and endurance exceeding 10¹⁴ cycles. Bit-line and word-line disturbance both held past 1 second at 85°C.

NEO's earlier 3D X-DRAM disclosures described 1T1C and 3T0C IGZO-based cells targeting up to 512Gb density per die, far beyond the capacity ceiling of conventional planar DRAM. Independent analysts framed the silicon result as a genuine inflection point. "As conventional DRAM scaling approaches its limits, the industry is shifting toward 3D architectures," said Jeongdong Choe, senior technical fellow and SVP at TechInsights, comparing the moment to the industry's transition to 3D NAND a decade ago.

Why It Runs on 3D NAND Infrastructure

The central claim — and the reason this story matters to the equipment supply chain — is manufacturability. NEO states the POC chips demonstrate that 3D X-DRAM can be built using existing 3D NAND infrastructure: established deposition and etch equipment, established materials, and cost-efficient processes already running at volume. With 3D NAND now exceeding 300 layers in production, that shared toolset is mature and depreciated.

"By leveraging established 3D NAND manufacturing processes and ecosystem, we aim to bring 3D DRAM to reality sooner," said Andy Hsu, founder and CEO of NEO Semiconductor. The company is pursuing a licensing and partnership model rather than building its own fabs, and says it is in active discussions with memory and semiconductor partners.

The Stan Shih Investment and Taiwan Ecosystem

The POC was developed with National Yang Ming Chiao Tung University (NYCU) and its Industry-Academia Innovation School, and was fabricated and tested at the National Institutes of Applied Research–Taiwan Semiconductor Research Institute (NIAR-TSRI). Jack Sun — SVP at NYCU, dean of the innovation school, and a former CTO of TSMC — said the work "confirms the feasibility of implementing advanced memory technologies using mature processes."

Stan Shih's backing adds weight from one of Taiwan's most established technology figures. "NEO's 3D DRAM is expected to play a key role in future system architectures," Shih said, citing Taiwan's semiconductor ecosystem as the enabler of the result.

What Comes Next

NEO's next phase covers array-level implementation, multi-layer test chip development, and deeper engagement with leading memory companies on co-development. CEO Andy Hsu is scheduled to give a keynote on the 3D X-DRAM POC at the FMS: Future of Memory and Storage conference, August 4–6, 2026, in Santa Clara, California.

A move from single-device POC to a working memory array is the real test, and commercialization timing depends on partner adoption. But the result puts a credible 3D DRAM candidate on the same roadmap conversation as conventional DRAM scaling and high-bandwidth memory.

What This Means for Plasma Processing and Thin Film Deposition

3D X-DRAM is, structurally, a deposition- and etch-defined device. Like 3D NAND, it is built by alternately stacking conductive and insulating films and then opening high-aspect-ratio vertical structures through that stack. A 300-plus-layer film stack means hundreds of PECVD and CVD deposition steps for the oxide/nitride layers, and the cell itself relies on conformal ALD for gate dielectrics and channel layers — plus PVD or ALD deposition of IGZO, the oxide-semiconductor channel material at the heart of NEO's design.

The architecture is equally plasma-etch intensive. Cutting deep, high-aspect-ratio holes and slits through a tall film stack is the hardest step in 3D NAND today, and 3D DRAM inherits that challenge directly. Demand here flows to advanced dielectric etch, cryogenic and pulsed-plasma etch processes, and the plasma sources, RF power delivery, and process monitoring that keep etch profiles vertical at extreme depth.

The supply-chain takeaway is that NEO's "use the 3D NAND toolset" pitch points new memory volume at the same deposition and etch platforms — not a separate, unproven equipment class. That is good for the installed base of ALD, CVD, PECVD and high-aspect-ratio etch tools, and for the components feeding them: plasma sources, sputtering targets and IGZO source materials, vacuum components, precursor and gas delivery systems, and in-line process monitoring. If 3D DRAM follows the 3D NAND playbook, every added layer multiplies deposition and etch passes — and the equipment supply chain scales with it.