Jensen Huang Flies to TSMC to Lock In Vera Rubin Capacity as Nvidia's Six-Chip Platform Pushes CoWoS Packaging Toward 130,000 Wafers a Month

By NineScrolls Team · 2026-05-27 · 5 min read · Industry

Why Huang Landed in Taipei Three Days Before His Keynote

Nvidia CEO Jensen Huang arrived at Taipei's Songshan Airport on Saturday, May 23, ahead of his GTC Taipei keynote on June 1 and the Computex 2026 show that runs June 2–5. He told reporters he had "a lot to do" — an understatement, given that the central purpose of the trip was a meeting with TSMC Chairman C.C. Wei to lock in production capacity for Nvidia's next-generation Vera Rubin platform, which Huang calls "the largest product launch, probably in the history of Taiwan."

The visit was not about silicon supply. It was about whether Taiwan's packaging lines can assemble Vera Rubin systems fast enough to meet demand. Huang confirmed in Taipei that the ramp — which overlaps with the tail end of Grace Blackwell GB300 production — creates "a very busy second half" for the island's supply chain.

Vera Rubin: A Six-Chip System With Two Million Parts

Vera Rubin is the most operationally complex product Nvidia has ever built. It is a six-chip system: the Vera CPU, the Rubin GPU, an NVLink 6 switch, a ConnectX-9 SuperNIC, a BlueField-4 DPU, and a Spectrum-X Ethernet switch. Every chip in the platform is new, an approach Huang describes as unprecedented in the company's history.

Each NVL72 rack configuration connects 36 Vera CPUs and 72 Rubin GPUs over sixth-generation NVLink, contains nearly two million parts, and draws on roughly 150 Taiwanese supply-chain partners to assemble. Nvidia claims the platform delivers 3.5 times the training performance and five times the inference performance of its Blackwell predecessor, while cutting inference cost to one-seventh. The Vera Rubin NVL72 won both a Golden Award and the Sustainable Tech Special Award at Computex 2026, where its cable-free, fanless modular tray design — cutting assembly from two hours to five minutes per compute tray — and 100% liquid-cooled architecture were highlighted.

The Bottleneck Is Packaging, Not Silicon

The constraint Huang's TSMC meeting was built to address is advanced packaging. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) process integrates a GPU or CPU die with high-bandwidth memory into the unified package Nvidia's accelerators require. Without it, even a flawlessly fabricated 3nm wafer cannot become a functional AI chip.

TSMC is executing one of the most aggressive capacity expansions in semiconductor history, scaling CoWoS output from roughly 35,000 wafers per month in late 2024 toward a projected 120,000 to 140,000 wafers per month — about 130,000 — by the end of 2026. That is a nearly four-fold increase in under two years, on a line growing at an estimated 80% compound annual rate. Even so, C.C. Wei has said publicly that CoWoS capacity "remains sold out through 2025 and into 2026."

Nvidia has reportedly pre-committed more than half of TSMC's available CoWoS capacity through 2027, with one analysis putting its 2026 booking near 595,000 wafers — roughly 60% of global demand — including about 510,000 wafers of the CoWoS-L variant used for Rubin GPUs and Vera CPUs. The Huang–Wei meeting was about converting that lock-in into the specific allocation commitments that turn Vera Rubin's production schedule into actual shipments.

The Numbers Behind the Capacity Scramble

The urgency is grounded in demand. Three days before landing in Taipei, Nvidia reported record Q1 fiscal 2027 revenue of $81.62 billion, an 85% year-over-year increase. Data center revenue — now 90% of the company's total — reached $75.2 billion, up 92% from a year earlier. Nvidia guided Q2 fiscal 2027 revenue to roughly $91 billion, authorized an additional $80 billion in share buybacks, and raised its quarterly dividend from $0.01 to $0.25 per share.

Notably, that guidance assumes zero China data center compute revenue, a market where Nvidia's share has collapsed from about 95% to effectively nothing under U.S. export controls. The strategic implication is that Taiwan's supply chain — not China — must now absorb essentially all of Nvidia's growth, which is exactly why packaging allocation has become the company's most pressing operational question.

What This Means for Plasma Processing and Thin Film Deposition

For the NineScrolls product category, the Vera Rubin ramp is a direct demand signal, because the CoWoS bottleneck is fundamentally a deposition-and-etch bottleneck. Building an interposer and stacking dies onto it is one of the most plasma- and film-intensive flows in the industry. Through-silicon via (TSV) formation depends on deep reactive-ion etching — high-aspect-ratio plasma etch that carves narrow vertical vias through silicon. Those vias are then lined and sealed using ALD barrier and liner layers and PECVD dielectric passivation before being filled, and redistribution layers are built up with PVD seed deposition and sputtered metals. Every CoWoS wafer that TSMC adds to its 130,000-per-month target multiplies these exact process steps.

As CoWoS-L scales for a six-chip system carrying nearly two million parts, the deposition and etch content per package only rises: larger interposers, more interconnect layers, finer RDL pitch, and tighter overlay all add plasma activation, conformal ALD, and high-precision etch steps. This favors precisely the tool set this market serves — ALD and PEALD for atomic-scale conformality, PECVD and CVD for dielectrics and passivation, and PVD and sputtering for seed layers, barriers, and RDL metals.

The pull continues down the equipment supply chain NineScrolls operates in. More plasma etch and deposition cycles per wafer mean firmer demand for the plasma sources and RF power delivery that strike and sustain those discharges, the sputtering targets consumed in PVD, the vacuum components and gas-delivery systems that feed every chamber, and the process-monitoring hardware that holds uniformity across high-aspect-ratio vias. When the CEO of the world's most valuable chip company flies to Taiwan specifically to secure packaging capacity, the message for the etch and deposition supply chain is unambiguous: advanced packaging is now the gating step of the AI buildout, and its growth runs straight through plasma processing and thin film deposition.