Intel EMIB-T Hits the Fab Floor in 2026: TSV Bridge Packaging for HBM4 Pulls New Demand for Deep Reactive Ion Etch and PECVD Liners

By NineScrolls Team · 2026-05-05 · 5 min read · Industry

What Changed: EMIB-T Moves From Disclosure to Fab Rollout

Intel's EMIB-T — Embedded Multi-Die Interconnect Bridge with Through-Silicon Vias — is moving from technology disclosure to production fab rollout this year, according to Tom's Hardware. EMIB-T is the first EMIB variant that routes signals through the silicon bridge with TSVs instead of around it, and it is the packaging vehicle Intel is pointing at HBM4-class accelerators.

Intel has set the 2026 reticle-scale target at roughly 8x and a 2028 target at 12x or more, with a top-end EMIB-T package envelope of 120 mm by 180 mm capable of hosting more than 38 bridge dies and over 12 reticle-sized compute or memory tiles, per Tom's Hardware and EDN coverage of Intel's IEDM disclosures.

Inside the EMIB-T Bridge Die: DRIE TSVs and PECVD Liners

The added "T" in EMIB-T is silicon-side, not assembly-side. Each bridge die now carries vertical copper through-silicon vias that pass power and signals straight from the package substrate to the dies above, instead of forcing currents to wrap around the bridge. Intel's published specs put the bump pitch at 45 microns today with a roadmap to 35 and 25 microns, with UCIe-A interconnect running at 32 Gb/s per pin and around 0.25 picojoules per bit, according to Tom's Hardware.

Building those TSVs is a wafer-front-end-class process flow grafted onto a packaging part. The high-aspect-ratio holes are produced by deep reactive ion etching (DRIE) — a Bosch-style alternating SF6 etch and C4F8 passivation cycle — and the sidewalls are coated with a thin silicon dioxide dielectric liner deposited by chemical vapor deposition, with PECVD typically chosen for its lower thermal budget. A barrier and seed stack is then laid down by physical vapor deposition before the via is filled with electroplated copper and planarized.

HBM4 Power Delivery Pulls in Google and Amazon

EMIB-T's pitch to AI-accelerator designers is concrete: it solves the power delivery problem that kept standard EMIB out of HBM4-class sockets. Per Tom's Hardware, the TSVs cut resistive loss in the high-current path, and a copper grid embedded in the bridge acts as a ground plane to suppress noise during sudden core ramps.

TrendForce reported on April 7 that Intel's advanced packaging is gaining traction against TSMC's CoWoS, with Google and Amazon weighing EMIB adoption for their TPU and Trainium ASICs respectively. Intel itself has said on recent calls that customer evaluations of its packaging stack are accelerating in tandem with 14A and 18A engagements.

Capacity Footprint: Rio Rancho, Malaysia, and Amkor

The capacity buildout is multi-site. Intel's Fab 9 and Fab 11X in Rio Rancho, New Mexico were the first to enter mass production for Intel's 3D advanced packaging technologies, per TrendForce. A new advanced-packaging and assembly complex in Malaysia is slated to come online in 2026 to add high-volume EMIB and EMIB-T capacity outside the United States.

Intel has also moved part of the assembly line outside its own walls. Amkor will roll out EMIB assembly in Korea, Portugal, and an upcoming Arizona facility under a strategic partnership, marking Intel's first material outsourcing of advanced packaging.

Context: CoWoS Capacity Tightness Opens the Window

The timing matters. TSMC's CoWoS capacity remains the gating supply for AI accelerator packaging in 2026, and hyperscalers shopping designs for HBM4-class memory have been looking for second sources. Intel's pitch — that EMIB-T can scale to 12x reticle by 2028 with HBM4 and HBM5 support and a credible UCIe roadmap — lands during a window when buyers are unusually willing to qualify a new packaging house.

Intel CFO David Zinsner has confirmed Intel is holding operating expenses flat near $16 billion into 2026 and steering investment toward 18A ramp, 14A development, AI products, and advanced packaging — a budget shape that reads as protecting EMIB-T capex even as other programs are cut. On April 30, Digitimes reported that Kevork Kechichian's reorganization has already killed three projects in two months as part of a multi-year reset.

What This Means for Plasma Processing and Thin Film Deposition

EMIB-T is, mechanically, a packaging program that buys wafer-fab tools. Every bridge die produced is a small wafer of TSV, dielectric, barrier, and metal — so the rollout pulls a packaging-shaped order book through the equipment supply chain.

For plasma processing, the load is concentrated in deep reactive ion etch. Bosch-process DRIE chambers from Lam Research, SPTS (KLA), Plasma-Therm, and Oxford Instruments handle the TSV holes, and demand scales linearly with bridge area and density. Atomic-scale etch and post-etch residue removal also pull through plasma cleaning systems and remote-plasma strippers. As bump pitch tightens to 35 and then 25 microns, sidewall scallop control and notch suppression become the binding specs, which favors fast-switching plasma sources of the kind Lam markets as DirectDrive.

For thin film deposition, EMIB-T is a multi-tool job. PECVD systems lay down the SiO2 sidewall liner at low thermal budget; ALD fills in for ultra-conformal liner refinement and barrier work as aspect ratios climb; PVD sputters the Ta/TaN diffusion barrier and copper seed; and electroplating plus CMP closes the loop. Applied Materials' Endura PVD platform, Lam's SABRE electroplating tools, and ALD systems from ASM International, Applied Materials, and Tokyo Electron all sit on the bill of materials.

For the broader equipment supply chain, the story is incremental but durable. TSV-grade gas delivery (SF6, C4F8, NH3, silane, TEOS), high-throughput vacuum components, RF generators and matching networks, in-situ FTIR and OES process monitoring, and target manufacturing for copper, tantalum, and titanium nitride all see steady pull. With TSMC's CoWoS capacity tight and hyperscalers actively qualifying Intel's bridge stack for HBM4 sockets, the EMIB-T rollout is one of the few 2026 catalysts that converts AI accelerator demand directly into orders for plasma etch chambers and thin film deposition systems.