Huawei Unveils Tau Scaling Law and LogicFolding 3D-Stacked Architecture, Targets 1.4nm-Equivalent Density by 2031 Without EUV

By NineScrolls Team · 2026-05-31 · 5 min read · Industry

1. The Shanghai Keynote

On May 25, 2026, He Tingbo, chairman of Huawei's HiSilicon semiconductor division and a Huawei board member, delivered a keynote titled "New Semiconductor Path in Practice" at the IEEE International Symposium on Circuits and Systems (ISCAS) 2026 in Shanghai. The talk laid out Huawei's roadmap for evolving advanced silicon without access to the leading-edge lithography tools that U.S. export controls keep out of China.

Huawei used the keynote to introduce two linked concepts: the Tau (τ) Scaling Law, proposed as a successor framework to Moore's Law, and LogicFolding, a chip architecture that stacks logic circuits onto a dual-layer framework. Huawei said it has already designed and mass-produced 381 chips using these principles over the past six years, and that the first Kirin processor built on LogicFolding will ship in fall 2026.

Following the announcement, shares in Semiconductor Manufacturing International Corp. (SMIC), China's largest contract chip manufacturer, jumped more than 19%.

2. What the Tau (τ) Scaling Law Actually Says

Tau Scaling reframes the chip-improvement question. Instead of shrinking the transistor (geometric scaling), it focuses on shortening the time constant τ — the resistance-capacitance delay that limits how fast signals propagate through devices and interconnects. Huawei argues this is the right knob to turn now that geometric scaling has hit physical limits and diminishing economic returns.

Per the official Huawei release, the framework attacks τ at four levels: device (RC of transistors and interconnects), circuit (LogicFolding layout), chip (full-stack software/architecture/silicon co-design), and system (UnifiedBus interconnect protocol with unified memory addressing).

3. LogicFolding: Folded, Dual-Layer Logic Circuits

LogicFolding is the circuit-level expression of Tau Scaling. Rather than laying logic out on a single plane and shrinking the transistors, LogicFolding physically folds and stacks logic circuits onto a dual-layer framework. The aim is to break the boundaries of conventional 2D layout, shorten critical-path wiring, and cut the resistive and capacitive load along signal propagation paths.

This is a "true-3D" approach in Huawei's terminology: the multilayer chip is optimized as a single vertical structure, not as two flat layers stitched together after the fact. Huawei said it intends to scale the same architecture to its Ascend AI accelerators, with deployment in AI data centers targeted by 2030.

4. The Numbers Huawei Is Putting Forward

For the first LogicFolding Kirin, expected in the Huawei Mate 90 series this fall, Huawei is claiming a 53.5% increase in transistor density to 238 MTr/mm², a 41% increase in performance-core power efficiency, and a 12.7% boost in maximum clock frequency to 3.1 GHz, all relative to conventional SoC design. Independent benchmark numbers have not yet been released.

The longer-term roadmap targets 400+ MTr/mm² and 5.00 GHz clocks by 2031, with Huawei describing the result as "equivalent to a 14 Å (1.4 nm) process." Crucially, Huawei is saying it can hit that density target while continuing to fabricate on more mature 5 nm- and 7 nm-class processes — not by inventing a new lithography node. For context, TSMC's own 1.4 nm node (A14) is targeted for mass production in 2028.

5. Why This Is a Sanctions Story

The U.S. and the Netherlands have progressively tightened controls on EUV lithography tools and other advanced wafer-fab equipment shipped into China. Without EUV, Chinese fabs are blocked from the conventional path to sub-5 nm logic. LogicFolding is Huawei's wager that vertical stacking, plus aggressive RC engineering, can extract another generation of performance from mature DUV-class nodes that SMIC and other Chinese foundries already run.

Omdia analyst Lian Jye Su told the Wall Street Journal it remains to be seen whether Huawei can hit the targets, but called it "an alternative path forward, and a breakthrough Huawei managed to find while facing supply chain challenges." The market reaction — a 19% single-day move in SMIC — suggests investors are treating the announcement as more than a research curiosity.

6. What This Means for Plasma Processing and Thin Film Deposition

LogicFolding moves the front line of advanced logic from lithography to deposition, etch, and bonding. That shift directly raises the value of process equipment NineScrolls customers care about.

Thin film deposition systems. A dual-layer logic stack multiplies the number of dielectric and metal layers per finished device. Each folded layer needs ultra-thin, defect-free interlayer dielectrics, barrier and liner metals, and bonding-interface films — work done by PECVD, ALD, PVD, and sputtering tools. ALD in particular benefits, because angstrom-class film control on bonding interfaces and high-aspect-ratio inter-tier vias is what makes wafer-to-wafer stacking electrically reliable. Industry forecasts already point to PECVD as the largest CVD segment at roughly 35% share; vertical logic architectures push that share higher.

Plasma processing and etch. True-3D layouts require dense vertical interconnects — through-silicon vias (TSVs), through-dielectric vias, and increasingly nano-TSVs — all of which are high-aspect-ratio plasma etch problems. Cryogenic HF, fluorocarbon, and atomic-layer etch processes that the leading-edge etch vendors have been pushing for 3D NAND and GAA logic apply directly here. Plasma activation of bonded surfaces is another critical step: hybrid bonding yields depend on a clean, terminated oxide surface created by low-damage plasma treatment before alignment and anneal.

Equipment supply chain. More layers and more etch/deposition steps per die translate into more cycles on plasma sources, RF power supplies, magnetrons, sputter targets, vacuum chambers, mass-flow controllers, precursor delivery, and in-line process monitoring — the components and subsystems that move through every fab regardless of whose architecture is on top. The shift toward stacking-first scaling, run on mature nodes, also reshapes demand patterns: Chinese domestic equipment makers (Naura, AMEC, Piotech, ACM) that already serve 5 nm- and 7 nm-class lines stand to gain wafer starts, while Western tool vendors (Applied Materials, Lam Research, Tokyo Electron, ASM International) are already positioning ALD, PECVD, advanced etch, and hybrid-bonding platforms exactly where this architecture lives.

If Huawei executes against its roadmap, the bottleneck for advanced logic shifts from "do you have EUV?" to "how good is your deposition-etch-bond stack?" That is the question NineScrolls' equipment niche is built to answer.