Deposition and Etch Intensity Is Doubling as 3D NAND Races Toward 1,000 Layers — SEMI Sees $136 Billion in Memory Equipment Spending Through 2028

By NineScrolls Team · 2026-05-25 · 7 min read · Industry

The Throughline Behind the Equipment Boom: Intensity Is Doubling

The record quarters reported across the wafer-fab equipment sector this spring share a single technical cause, and it is not simply that fabs are buying more tools. It is that each new generation of chip needs far more deposition and etch per wafer than the one before. As semiconductors move from flat designs to stacked, three-dimensional architectures, deposition and etch intensity is expected to rise by roughly a factor of two, according to Lam Research Chief Technology Officer Vahid Vahedi, who laid out the shift in an April 2026 technical briefing.

The reason is geometric. Going 3D means building structures that are taller, more complex, and defined by smaller features — and that demands deeper etch to carve them and more precise, conformal deposition to fill and line them. "Everything — NAND, Logic, DRAM, and packaging — is going 3D," Vahedi wrote, and every one of those transitions pulls the same two process steps to the center of the manufacturing flow. For a generation of chips driven by artificial-intelligence demand, etch and deposition have become the gating technologies.

3D NAND Past 400 Layers, Heading to 1,000

NAND flash is the clearest illustration. The evolution of memory has become, in effect, a vertical space race: the number of stacked layers has already passed the 400-layer mark and the industry is openly developing toward 1,000-layer structures. Because the way to add capacity is now to stack more layers rather than shrink each one, the burden falls squarely on etch and deposition. Every additional layer is another film to deposit and another increment of depth to etch through.

The aspect ratios involved are extreme. Today's 3D NAND channel-hole etch runs at roughly 50:1, with the industry pushing toward 100:1 as stacks grow — etching deep, near-perfectly vertical holes through alternating silicon-oxide and silicon-nitride films without tilting or distorting. The deeper the etch, the slower it typically goes, which is why Lam and others have turned to cryogenic etching that can run about 2.5 times faster than conventional approaches that could otherwise take up to an hour per step. One industry analysis put hard numbers on the equipment pull: as a representative 3D NAND device scales from 32 to 128 layers, the share of etch tools in the line rises from about 34.9 percent to 48.4 percent of equipment usage, because the number of channel-hole, slit, and contact-via steps scales almost directly with layer count.

DRAM Goes Vertical and HBM Stacks Higher

DRAM, planar for decades, is now beginning the same transition. Memory makers are moving from 6F² to 4F² cell designs as a step toward fully 3D DRAM, where cells rotate ninety degrees and stack vertically. That path demands high-aspect-ratio etch to form channels, atomic layer deposition (ALD) to fill them, copper plating to bond CMOS wafers to the array, and new deposited metals such as molybdenum to hold down resistance as wordlines shrink. The verticality is even more punishing than NAND: Lam expects aspect ratios eventually reaching 200:1 in 3D DRAM, where, across a 10-micrometer stack, the allowable profile tilt drops below 0.1 degrees. High-volume tools for those geometries do not yet exist and will have to be co-developed by equipment makers, materials suppliers, and device manufacturers.

High-bandwidth memory is the 3D shift already in volume. By stacking 4 to 16 DRAM dies and connecting them with dense through-silicon vias — up to 2,048 interconnects in HBM4 — HBM multiplies the number of etch, deposition, and bonding steps per device. Demand is running ahead of supply: research firm TrendForce reported that some vendors' HBM capacity for all of 2026 is already fully reserved, a booking pattern that flows straight through to the tool makers serving etch, deposition, bonding, and inspection.

The Dollars: $136 Billion in Memory Tools Through 2028

The spending math follows the process intensity. SEMI projects that global equipment expenditure tied to the memory and storage segment will reach roughly $136 billion between 2026 and 2028, with 3D NAND alone accounting for more than 40 percent of that figure. Deposition's growing share is visible in the historical mix: Tokyo Electron has noted that thin-film deposition equipment made up about 18 percent of flash-line capital spending in the 2D era and rises to roughly 26 percent in the 3D era — and climbs further as layer counts and aspect ratios increase.

The top-line market reflects the same pull. SEMI's year-end forecast put total semiconductor equipment sales at a record $133 billion in 2025, up 13.7 percent, and expects $145 billion in 2026 and $156 billion in 2027. Within that, wafer-fab equipment — the deposition, etch, and lithography heart of the market — is projected to grow about 9 percent to roughly $126 billion in 2026 and another 7.3 percent to about $135 billion in 2027, with memory the strongest driver. The geographic center of that spending is shifting toward the memory makers: SEMI expects South Korea to return to the world's second-largest equipment-spending market in 2026 at about $29.7 billion, up 27.2 percent year over year, behind only mainland China.

A Localization Race Around Etch, Deposition, and Bonding

Because etch and deposition now sit at the choke point of memory scaling, they have become the focal point of China's equipment-localization push. Chinese suppliers are positioning across exactly the segments the 3D transition rewards. AMEC has extended its capacitively coupled plasma etch tools into high-aspect-ratio 3D NAND etching and reported that LPCVD and ALD systems for advanced memory and logic have entered the market. NAURA offers deep-silicon etch, thin-film deposition, thermal processing, and electroplating tools for memory manufacturing and is the domestic leader in PVD. Piotech has built out a PECVD, ALD, SACVD, and flowable-CVD deposition portfolio shipping to leading domestic foundries, while ACM Research is expanding from cleaning into a platform that now includes thin-film deposition.

The pattern matters beyond China. It confirms where the technical and commercial value of the memory build-out is concentrating — not in any single chip design, but in the deposition and etch process modules that every stacked device, foreign or domestic, has to pass through. As one industry survey framed it, the rapid iteration of 3D NAND, 3D DRAM, and HBM means demand for etch, thin-film deposition, and bonding equipment will keep compounding as the core support for the entire storage upgrade.

What This Means for Plasma Processing and Thin Film Deposition

This is the most direct demand signal there is for the NineScrolls product category, because the story is the product category. The intensity that is doubling is plasma etch and thin film deposition intensity. Higher NAND stacks mean more high-aspect-ratio plasma etch steps and more deposited films per wafer; the move toward cryogenic plasma etch to keep throughput up changes the chamber, the RF power scheme, and the temperature-control hardware around the plasma. The DRAM transition to 4F² and eventually 3D layers adds conformal ALD fill, PECVD liners and barriers, and HAR etch at tilt tolerances under a tenth of a degree.

Across deposition, the same shift favors precisely the tool set this market sells: ALD and PEALD for atomic-scale conformality in deep, narrow trenches; PECVD and CVD for the oxide-nitride stacks and dielectrics; and PVD and sputtering for metal gates, barriers, and the molybdenum and copper layers that 3D memory increasingly relies on. Perpendicular processing — etching and depositing sideways at ninety degrees, layer after layer — pushes ALD and atomic-layer etch capability well beyond what 2D devices ever required.

The pull runs all the way down the supply chain NineScrolls operates in. More plasma steps, deeper etch, and more deposition cycles per wafer mean firmer demand for the plasma sources and RF power delivery that strike and sustain those discharges, the sputtering targets consumed in PVD, the vacuum components and gas-delivery systems that feed every chamber, and the process-monitoring hardware that holds angstrom-level uniformity across 200:1 features. With SEMI pointing to $136 billion of memory-equipment spending through 2028 and intensity rising faster than wafer counts, the runway behind plasma processing and thin film deposition is structural, not cyclical — and it is being extended every time the industry adds another layer.