Applied Materials and EV Group Report 98% Yield on 450nm-Pitch Copper Hybrid Bonding Across 20 Million Interconnects at ECTC 2026

By NineScrolls Team · 2026-05-28 · 5 min read · Industry

The Result: 450nm Pitch, 98% Yield, 20 Million Links

At the 76th IEEE Electronic Components and Technology Conference (ECTC), running May 26–29 at the Grande Lakes resort in Orlando, Applied Materials and EV Group are presenting what they describe as the industry's first demonstration of 450-nanometer-pitch copper-to-copper hybrid bonding achieving 98% yield across 20 million interconnect links. The paper, "First Demonstration of 450nm Pitch Cu-Cu Hybrid Bonding with 98% Yield Across 20M Interconnects for Ultra-Dense 3D Integration" (Paper 18.4, Y. Trickett et al), is scheduled for Session 18 on Thursday, May 28.

The numbers matter because density and yield have been pulling against each other. Wafer-to-wafer hybrid bonding for the most advanced 3D memory and logic now requires sub-0.5-micron bond pitch, yield above 90% across via chains of up to 20 million links, and ultra-low leakage across the bond interface. Hitting 98% at a 450nm pitch across the full 20-million-link chain clears that bar and, the authors argue, lays the groundwork for scaling the bond pitch below 300nm.

How the Researchers Killed the Defect That Blocks Scaling

At these dimensions, parts-per-million-level open defects can meaningfully degrade wafer-level yield. The team used Electron Beam Absorbed Current (EBAC) analysis to locate those open defects, then turned to TEM-EELS analysis, which revealed a thin carbon-rich layer at the copper-copper bond interface. That contamination coincided with the presence of large, (111)-oriented copper grains on the top and bottom pads.

Eliminating the defect came down to controlling the metal itself. The paper details process optimizations spanning metallization, chemical mechanical polishing (CMP), plasma treatments, and post-bond annealing that together allowed the researchers to engineer the grain size and crystal orientation at the bond interface precisely enough to remove the defect. EV Group frames the result within a broader collaboration: it provides the complete wafer-to-wafer hybrid bonding process flow, anchored by its GEMINI FB automated production bonder, which it calls the de facto industry standard for hybrid and fusion bonding.

Why Hybrid Bonding Became the Industry's New Battleground

Hybrid bonding joins two wafers or dies by directly fusing their dielectric surfaces and copper pads without solder bumps, enabling far finer interconnect pitch and shorter electrical paths than micro-bumps allow. As AI and high-performance computing push 3D stacking harder, it has become a critical enabler for CMOS-bonded-to-array (CBA) memory designs, HBM stacks, chiplet integration, and 3D system-on-chip architectures.

The breadth of the ECTC 2026 program underscores how central this has become. The conference brings together more than 2,000 scientists and engineers, and hybrid bonding and heterogeneous integration dominate the technical sessions. Beyond the Applied Materials and EV Group result, KIOXIA is presenting a misalignment-correction technique for multi-stacked CBA structures in 3D NAND with sub-800nm-pitch bonding pads, and ASML is detailing a die-distortion-correction method targeting sub-80nm die-to-wafer bonding overlay.

The Race Below 300nm: SiCN, 50nm Overlay, and Warped Wafers

The 450nm result is one step on a roadmap that is already pushing tighter. In a second jointly authored paper at the same conference, "Process Integration for 300nm-Pitch Hybrid Bonding with SiCN: 50nm Overlay, Fine-Grain Cu Metallurgy, and Reliability Assessment" (Paper 26.4 session, Friday, May 29), Applied Materials and EV Group address 300nm-pitch bonding using a silicon carbonitride (SiCN) bonding dielectric, with 50nm overlay and fine-grain copper metallurgy.

The dependencies for going finer are sobering. KIOXIA's work highlights that warped wafers — common in 3D NAND, where complex, non-uniform stress distributions develop — drive misalignment and bonding failures, while ASML's contribution shows how singulation-induced stress relaxation distorts dies before they are even placed. Closing the loop on pitch, overlay, and yield simultaneously is what separates a conference demonstration from a high-volume manufacturing process — and it is exactly that integration work that the Applied Materials and EV Group papers target.

What This Means for Plasma Processing and Thin Film Deposition

Hybrid bonding is, at its core, a deposition-and-surface-engineering problem, which puts it squarely in the NineScrolls product category. The bond interface is built from a dielectric film — increasingly SiCN deposited by PECVD — and a copper pad. Getting two such surfaces to fuse with 98% yield at 450nm pitch depends on the deposited film's quality and the surface state, which is why the ECTC paper lists plasma treatments alongside metallization, CMP, and annealing as the levers that eliminated the interface defect. Plasma activation of the bonding surfaces is what makes low-temperature direct bonding work at all.

The thin film deposition content is just as direct. The copper pads originate from PVD seed layers and electroplated fill; the bonding dielectric and any barrier and liner layers come from PECVD, CVD, and ALD/PEALD steps that must hold atomic-scale uniformity and thickness control across the wafer. The paper's finding that grain size and (111) crystal orientation determine whether the bond closes is a reminder that metallization process control — seed deposition, anneal, and the resulting microstructure — is now a yield-defining variable, not a back-end afterthought.

Down the equipment supply chain NineScrolls serves, finer-pitch hybrid bonding tightens every specification. Plasma activation chambers need stable plasma sources and well-controlled RF power delivery; PVD steps consume sputtering targets; every deposition and surface-prep chamber depends on vacuum components and precise gas delivery; and holding 20-million-link yield demands metrology and process monitoring that can catch parts-per-million defects. As the industry drives from 450nm toward sub-300nm pitch for HBM, 3D NAND, and chiplet stacks, the demand signal points straight at the plasma processing and thin film deposition tools — and the consumables and subsystems behind them — that make these atomically clean, atomically flat bonding interfaces possible.